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Xilinx Zynq-7020 interface high speed ADC AD9278&AD9670

Hello All,

Please help for my question about Xilinx Zynq-7020 interfacing AD9278 (12 bit, 8-channel, up to 65MSPS) or AD9670 (14 bit, 8-channel, up to 80MSPS).

1) Is Zynq-7020 (Artix-FPGA Fabric) able to interface and sample AD9278 or AD9670 8-channel data at 50MSPS?

2) If the answer to question 1) is yes, please help for possible instructions how to implement it. What are the maximum channels for Zynq-7020 (Artix-FPGA Fabric) to support at 50MSPS? like 16, 32 channels possibly?

Appreciate any help. Thank you.

Linda

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  • You need to use the BUFIO/BUFR on the clock, and all the rest FCO, DATA lines on the same bank.

    This allows you to use the SERDES with maximum IO bandwidth on these devices.

    At the output of the SERDES, transfer the data to the GCLK.

    You can try the core generator to give you a VHDL/Verilog template and then customize it from there.

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  • You need to use the BUFIO/BUFR on the clock, and all the rest FCO, DATA lines on the same bank.

    This allows you to use the SERDES with maximum IO bandwidth on these devices.

    At the output of the SERDES, transfer the data to the GCLK.

    You can try the core generator to give you a VHDL/Verilog template and then customize it from there.

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