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Xilinx Zynq-7020 interface high speed ADC AD9278&AD9670

Hello All,

Please help for my question about Xilinx Zynq-7020 interfacing AD9278 (12 bit, 8-channel, up to 65MSPS) or AD9670 (14 bit, 8-channel, up to 80MSPS).

1) Is Zynq-7020 (Artix-FPGA Fabric) able to interface and sample AD9278 or AD9670 8-channel data at 50MSPS?

2) If the answer to question 1) is yes, please help for possible instructions how to implement it. What are the maximum channels for Zynq-7020 (Artix-FPGA Fabric) to support at 50MSPS? like 16, 32 channels possibly?

Appreciate any help. Thank you.

Linda

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  • It depends-- is this an interposer based design on ZC702 or Zed -- or your own??

    If you are looking for the raw bandwidth without any board level constraints, refer to the switching characteristics of the device - it will tell you the maximum IO bandwidth. Lowest is around 950 (DDR), 600 (SDR) - so 780Mbps (AD9278 @65) seems sufficient.

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  • It depends-- is this an interposer based design on ZC702 or Zed -- or your own??

    If you are looking for the raw bandwidth without any board level constraints, refer to the switching characteristics of the device - it will tell you the maximum IO bandwidth. Lowest is around 950 (DDR), 600 (SDR) - so 780Mbps (AD9278 @65) seems sufficient.

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