Format of data at DAC I & Q inputs

Hi,

In the following code, there is a sine wave lookup table

https://github.com/analogdevicesinc/no-OS/blob/ecf8147b6e1c63fd649fea148482a6712d657a9c/ad9361/sw/dac_core.c#L183

const uint16_t sine_lut[32] = {
0x000, 0x031, 0x061, 0x08D, 0x0B4, 0x0D4, 0x0EC, 0x0FA,
0x0FF, 0x0FA, 0x0EC, 0x0D4, 0x0B4, 0x08D, 0x061, 0x031,
0x000, 0xFCE, 0xF9E, 0xF72, 0xF4B, 0xF2B, 0xF13, 0xF05,
0xF00, 0xF05, 0xF13, 0xF2B, 0xF4B, 0xF72, 0xF9E, 0xFCE
};

Q01: In what format are these 16-bit words represented in? Is it 2's complement?

Q02: If I were to feed each word, directly from an HDL block (rather than a DMA), by connecting a test HDL block to the DAC I & Q inputs, what clock frequency should I use?

Q03: What does the left-shift <<20 and <<4 for the I & Q inputs achieve?

data_i1 = (sine_lut[index_i1 / 2] << 20);
data_q1 = (sine_lut[index_q1 / 2] << 4);

Regards,

Elvis Dowson

  • Hi Elvis,

    The AD9361 integrates two 12-bit DACs. However, the HDL core accepts 16-bit inputs - because of this, the values are left shifted by 4. They are using the 2's complement format - the REG_CNTRL_2 - DATA_FORMAT is also set to 2's complement (0x0) (http://wiki.analog.com/resources/fpga/xilinx/hints/pcore_register_map#dac_common).

    Regarding your second question: are you referring to the I and Q data sample rate?

    Regards,

    Dragos

  • Hi Dragos,

    For the AD9122 DAC on the AD-FMCOMMS1-EBZ, it accepts data from the VDMA, which is 64-bits wide.

    In the HDL sources, why is dac_data_i0 and dac_data_i1 assigned to the same value? Is there any significance for the 4 I&Q pairs?

    https://raw.github.com/analogdevicesinc/fpgahdl_xilinx/master/cf_lib/edk/pcores/axi_ad9122_v1_00_a/hdl/verilog/axi_ad9122_core.v

    // dac outputs
    
      always @(posedge dac_div_clk) begin
        if (dac_datasel_s[3:1] == 3'd1) begin
          dac_data_i0 <= dac_vdma_data_s[15: 0];
          dac_data_i1 <= dac_vdma_data_s[15: 0];
          dac_data_i2 <= dac_vdma_data_s[47:32];
          dac_data_i3 <= dac_vdma_data_s[47:32];
          dac_data_q0 <= dac_vdma_data_s[31:16];
          dac_data_q1 <= dac_vdma_data_s[31:16];
          dac_data_q2 <= dac_vdma_data_s[63:48];
          dac_data_q3 <= dac_vdma_data_s[63:48];
    

    Regards,

    Elvis Dowson

  • Hi,

    Would anyone happen to know what the 4 I&Q pairs for the AD9122 DAC in the HDL does?

    I wrote my own AXI4-Stream IQ generator with a 64-bit data bus, replacing the VDMA, and packed the data stream with i samples [15:0], q samples [31:16] and padded the rest with zeros [63:32]. I was able to get the sine wave and cosine waves on the ADC debug probe output, in Vivado-2013.2 Analyzer.

    Now the thing is I can't find anywhere in the AD9122 data sheet, a reference to 4 I&Q pairs, and would like to know

    a. Why the dac_data_i0 and i1 are fed the same signals

    b. What dac_data_i3 and i4 are supposed to be?

    Regards,

    Elvis Dowson

  • Elvis,

    That is meant for a place holder only. The DAC only needs one set of I/Q.

    The reason for that is - VDMA problems. In order to meet the DAC bandwidth at the full rate it would require that the bus be 128bits wide. This made the VDMA hang. That needs to be replaced by an interpolator- but it fell into the bottom of our to-do list.

    If you have your own IQ generator, all you need to do is make that 128 bits wide and change the code as follows.

    1.       dac_data_i0 <= dac_vdma_data_s[15: 0]; 
    2.       dac_data_i1 <= dac_vdma_data_s[47:32]; 
    3.       dac_data_i2 <= dac_vdma_data_s[79:64]; 
    4.       dac_data_i3 <= dac_vdma_data_s[111:96];
    1.       dac_data_q0 <= dac_vdma_data_s[31:16]; 
    2.       dac_data_q1 <= dac_vdma_data_s[63:48]; 
    3.       dac_data_q2 <= dac_vdma_data_s[95:80]; 
    4.       dac_data_q3 <= dac_vdma_data_s[127:112]; 
  • Also, just to make things a little bit more clear-

    This is simply parallel samples- doesn't mean you need 4 sets of I/Q.

    It only mean that you need to get 4 samples of - 1 set of I/Q  - per clock.

    This is because of the SERDES modules. (4 to 1 serialization).