I'm having problems interfacing the AD9222 with an Altera Stratix-III FPGA. I developed an HSM connector-based daughter board for the Stratix-III development kit which has 2 AD9222 ADC's (16 LVDS channels). Incidentally, the SPI works perfect. The FCO and DCO are routed to input clock pins, and the FCO can only be routed to a PLL (limitation of the board).
Is there anyone who has done this before and/or has a sample design I may see? I'm using the ALTDDIO_IN mega-function block to bring in the LVDS channel data (just one at the moment) followed by five d-type flip-flops.
I divide the incoming FCO by 2 (using a PLL) to create an enable for the ALTDDIO_IN and the flip-flops. At this point I know I'm only getting half of the data and will process the other half later. I'd just like to get something to work solidly. I can walk a one across the input (using the user-pattern registers) until the last four bits. They are jumbled. For example, writing a 0x0008 results in a 0x000A, writing a 0x0004 results in a 0x0005, etc ...
Any help / guidance is appreciated. Is there a better way of handling this?
Please advise, thanks in advance,