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We are trying to use the FMCMOTCON2 reference design and we cannot understand why the signal "word_clock" is routed as shown in the below snapshot. I can see that the AD7401 module might need the signal for synchronization but I don't see why it goes beyond.
The output of the register becomes a clock for the hundreds of flops. We expected a "create_clock" in the constraints file to help the tool assess and constrain it . Does the reference design provide a create_clock or multicycle constraints or this is left to the user"