AD-FMCDAQ2-EBZ reference design from the ZCU102 platform to an ALINX AXU15EG (ZU15EG)

Hello ADI Team,

I am currently porting the AD-FMCDAQ2-EBZ reference design from the ZCU102 platform to an ALINX AXU15EG (ZU15EG) evaluation board. Since the AXU15EG is not officially supported, I used the ZCU102 design as a reference.

Hardware

• Carrier board: ALINX AXU15EG (XCZU15EG)

• FMC board: AD-FMCDAQ2-EBZ

• Vivado: 2023.2

• Vitis: 2021.2

• Software: ADI no-OS (bare-metal) 2023_r2 Release

Step 1 – Vivado Hardware Porting

I first created a Vivado 2023.2 project by starting from the ZCU102 DAQ2 reference design.

The modifications included:

• Replacing the ZCU102 board with the AXU15EG device.

• Updating all board constraints (.xdc) according to the AXU15EG FMC HPC connector.

• Verifying:

  • JESD204 transceiver lane mapping

  • Differential clock pins

  • SYSREF

  • SYNC signals

  • SPI signals

  • GPIO assignments

• The design was implemented successfully and the bitstream was generated without critical errors.

Step 2 – Bare-Metal Software

I then created a Vitis bare-metal application using the ADI no-OS framework.

The software is based on the standard FMCDAQ2 example application without major modifications except for the platform-specific BSP.

The application starts correctly until the initialization of the AD9523 clock generator.

The console output reports:

AD9523: SPI write-verify failed (0x00FF)!

The failure occurs during ad9523_setup().

Debug Information

The SPI initialization completes successfully.

The failure happens when the driver performs a write followed by a read-back verification.

The read-back value is:

0x00FF

instead of the expected value.

From debugging, the failure occurs inside:

ad9523_setup()

↓

ad9523_spi_write()

↓

ad9523_spi_read()

↓

SPI write-verify failed

What I Have Already Checked

• SPI pin assignments match the AXU15EG schematic.

• SPI clock, MOSI, MISO and CS are connected correctly.

• FMC connector routing has been verified.

• The FPGA bitstream programs correctly.

My Questions

• Has anyone successfully ported the FMCDAQ2 reference design to a non-supported Zynq UltraScale+ board?
• What could cause the AD9523 SPI read-back to always return 0x00FF?
• Are there any recommended debug steps to isolate whether the problem is hardware, HDL, or software?
• Any suggestions would be greatly appreciated.

Thank you.