Hello,
I'm working with the ADRV9371 evaluation board in no-os mode and trying to enable the FPGA_AUX_CLK output, which is routed to OUT2 of the AD9528. However, I'm not getting any clock signal on this output while other outputs work correctly.
Setup:
- Board: ADRV9371-W/PCBZ board;
- FPGA Board: Alinx Zynq Ultrascale Plus board;
- Bare-metal code, version 1.5.1.3565;
- Target output: OUT2 (FPGA_AUX_CLK/SYSREF1_OUT_P/N)
- Measuring through AC coupling capacitors C806 and C805 on the board
- OUT1 (Device Clock for FPGA) outputs 125 MHz correctly
- PLL1 and PLL2 are both locked
- All other outputs are functional
Problem:
- The signal does not reach the FPGA;
- OUT2 shows static 0.8-0.9V DC level on oscilloscope, measured it on C806 and C805;
Register Configuration for OUT2 (identical to working OUT1):
0x303 = 0x00 | 0x306 = 0x00
0x304 = 0x00 | 0x307 = 0x00
0x305 | 0x308 = 0x09
Output power:
0x501 (Channel Power-Down 1) = 0x00 (all channels enabled)
0x503 (LDO Enables 1) = 0xFF (all LDOs enabled)
I have a two questions:
1. Are there any additional registers or initialization steps required specifically for OUT2 that differ from other channels?
2. Could there be a hardware-specific routing issue on the ADRV9371 board with FPGA-AUX-CLK?
Thank you!
