SYSREF Pulse Width timing violation from IOB Placement constraint

Hi,

I'm pin verifying a Vivado project for a custom board which will connect with several AD9695 chips. (FPGA = xczu4cg-fbvb900-2-e). Vivado 2025.1

I have based the design off the ZCU102 - AD9695 example design.

When compiling for 1.3 GSPS Sample speeds (Device Clock = 325MHz) I get a Pulse Hold timing violation on sysref_reg. It looks like this is a limit of the RXTX_BITSLICE primitive in which 'sysref_reg' is placed due to a constraint in the jesd204_rx IP:

Generated jesd204_rx constraint:

# Make sure that the device clock to sysref skew is at least somewhat
# predictable
set_property IOB true \
[get_cells {i_lmfc/sysref_r_reg}]

In the example design I see sys ref is routed through a clock buffer (BUFG_GT), which causes the above constraint to be ignored.

Currently our SYSREF inputs are non clock capable. I'm wondering if the solution to this is to change the pins and route SYSREF through a clock buffer like the example design (although it would be a BUFG in our case).

Would routing sysref through a BUFG meet the requirement of predictable device clock to sysref skew mentioned in the constraint? Or could the constraint just be ignored without the clock buffer? (Or another solution?)

Thanks in advance