AD9361/FMCOMMS2 on Artix UltraScale+ custom board: RX captures all-zero, ad9361_dig_tune fails at every delay

Hello,

I'm having issues getting anything visible on the RX data lines coming into the Artix U+ FPGA that interfaces to the FMCOMMS2 AD9361 over FMC. I've got a softcore CPU running the no-os firmware, and SPI to the AD9361 works great, RX DATA_CLK is present and correct (l_clk is legit 61.44MHz).

The dig_tune() is completely broken on ever pair.

Here's what works:

• SPI: chip_id (0x037)=0x0A, all register R/W clean.
• All PLLs locked: bbpll_lock=1, rx_vco_lock=1, tx_vco_lock=1.
• ad9361_init() completes ("AD936x Rev 2 successfully initialized"); all calibrations pass (RX/TX BB filter, TIA, ADC, BB-DC, RF-DC, Tx quad).
• ENSM in FDD-active (REG_STATE lower nibble = 0xA), RX1_EN=1.
• RF/analog RX works: rx1_rssi shows real energy (symbol ≈ 10900, preamble ≈ 11150), rx1_rf_gain = 71 dB.
• RX DATA_CLK is live: recovered byte clock l_clk measures 61.44 MHz (the correct 1R1T LVDS DDR rate) via the core's clock monitor; adc_valid pulses continuously.
• IDELAY infrastructure reports healthy: refclk 300 MHz, fine tap ≈ 104 ps, ≈ 4.9 sw-taps/UI.
• Parallel-port config reads correct for LVDS DDR 1R1T: 0x010=0xC0, 0x011=0x00, 0x012=0x10.

Here's what I tried already:

1. Bad board/card — tried my FMCOMMS2 on a ZCU102 with the stock design and it worked.
2. Pin mapping — rx_clk/rx_frame/rx_data[5:0] LVDS assignments checked against both the carrier and FMCOMMS2 schematics; all are LVDS DIFF_TERM_ADV TERM_100.
3. Held in reset — ADC/DAC rstn=0x3 (released); IDDR capture primitives have reset tied off.
4. ENABLE/TXNRX / ENSM trigger — tried SPI ENSM=FDD and pin-control mode (ENABLE_ENSM_PIN_CTRL + level mode + ENABLE asserted). Both reach FDD-active (0xA); both give 0.
5. IDELAY calibration / sample phase — full dig_tune incl. the FPGA IDELAY sweep across taps 0–31 on all lanes; no passing window anywhere. Also tried ADC_INIT_DELAY=11 (per zcu102). No change.
6. IDELAY refclk — 300 MHz (the COUNT-mode value); core reports healthy tap resolution.
7. 1R1T vs 2R2T mode mismatch — ruled out: l_clk=61.44 MHz is the expected 1R1T rate, RX1_EN=1, core runs R1 (runtime adc_r1_mode). A framing mismatch would yield scrambled non-zero data, not static zero.
8. Simulation — ADI's fmcomms2 testbench (and my datapath sim) validate the capture logic with idealized timing (TX→RX loopback / injected ADC data) and pass; neither exercises real-silicon LVDS RX capture timing.

Here's a summary of the hdl and no-os Git repos I'm using:

ADI analogdevicesinc/hdl main @ 32e1f9c8 ("library/axi_ad485x: Fix simulation issue")

ADI analogdevicesinc/no-OS main @ 313b6a68 ("drivers: axi_core: axi_dmac: …")

So the ultimate questions:

1. If the RX DATA_CLK is present and correct but there's no transitions on rx_data and rx_frame, what's going on?
2. Are there known LVDS RX capture issues with the Artux Ultrascale+ that are different from the ZCU102 Zynq Ultrascale+ that I use as a model to build things for my board?

Please help

-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

This is my log I have when my board starts up:

[ad9361_no-os] NEORV32 + AD9361 driver starting...
[ad9361_no-os] Calling ad9361_init()...
ad9361_reset: by GPIO
... [BBPLL + clock chain + all calibrations completed OK] ...
ad9361_set_trx_clock_chain: 983040000 245760000 122880000 61440000 30720000 30720000
ad9361_rx_adc_setup : BBBW 8606895 : ADCfreq 245760000
ad9361_run_calibration: CAL Mask 0x80   # RX BB filter   -> OK
ad9361_run_calibration: CAL Mask 0x40   # TX BB filter   -> OK
ad9361_run_calibration: CAL Mask 0x1    # BB DC offset   -> OK
ad9361_run_calibration: CAL Mask 0x2    # RF DC offset   -> OK
ad9361_run_calibration: CAL Mask 0x10   # TX quad        -> OK
LO leakage: 1  Quadrature Calibration: 1 : rx_phase 26
ad9361_set_tx_atten : attenuation 0 mdB tx1=1 tx2=0
rx_adc: Successfully initialized (40960693 Hz)
ad9361_init : AD936x Rev 2 successfully initialized
[ad9361_no-os] ENSM -> FDD

--- RX capture probe (every stimulus reads exactly 0x0000) ---
PHASE 1  real RX (BIST off):           ADC_STATUS=0x05 link_ok=1; adc_valid 200/200 (100%); ch0_I/Q min=0 max=0
PHASE 2  BIST PRBS_INJ_RX (0x3F4=0x09): link_ok=1; adc_valid 200/200 (100%); ch0_I/Q min=0 max=0
PHASE 3  BIST + CHAN_CNTRL_3 pn_sel=9:  ch0_I/Q min=0 max=0
Chip TX-BB->RX-BB loopback (ad9361_bist_loopback(1), DAC PN9): ch0_I/Q min=0 max=0

--- ad9361_dig_tune(BE_MOREVERBOSE|DO_IDELAY), skipmode=1 (RX) ---
SAMPL CLK: 30720000 tuning: RX
  0:1:2:3:4:5:6:7:8:9:a:b:c:d:e:f:
0:# # # # # # # # # # # # # # # #
1:# # # # # # # # # # # # # # # #
ad9361_dig_tune_delay: Tuning RX FAILED!
RX Lane 0, window cnt 0, start 0, IODELAY set to 0   # rx_data[0]
RX Lane 1, window cnt 0, start 0, IODELAY set to 0   # rx_data[1]
RX Lane 2, window cnt 0, start 0, IODELAY set to 0   # rx_data[2]
RX Lane 3, window cnt 0, start 0, IODELAY set to 0   # rx_data[3]
RX Lane 4, window cnt 0, start 0, IODELAY set to 0   # rx_data[4]
RX Lane 5, window cnt 0, start 0, IODELAY set to 0   # rx_data[5]
RX Lane 6, window cnt 0, start 0, IODELAY set to 0   # rx_frame

--- RX-path diagnostic dump ---
[adc_status]
  l_clk_hz=61441040  (expect 61440000 for 1R1T LVDS DDR)
  idelay refclk_hz=300000000 fine_tap=104ps sw_step=1664ps ui=8137ps sw_taps_per_ui=4.89
  rstn=0x3 status=0x5 link_ok=1  pn_oos=1 pn_err=0
  ch0_I ctrl=0x051 status=0x02 data=0x0000  pn_oos=1 pn_err=0 hdr=0
  ch0_Q ctrl=0x051 status=0x02 data=0x0000  pn_oos=1 pn_err=0 hdr=0
[chip_status]
  parallel_port_conf  0x010=0xC0  0x011=0x00  0x012=0x10   (LVDS, DDR, 1R1T, level frame, IQ swap)
  state (0x017)=0x1A  -> ENSM=FDD (0xA)
  RX1_EN=1 RX2_EN=0   TX1_EN=1 TX2_EN=0
  chip_id (0x037)=0x0A   bbpll (0x05E)=0x81 lock=1
  rx_cp_vco (0x247)=0x02 rx_vco_lock=1   tx_cp_vco (0x287)=0x02 tx_vco_lock=1
  rx1_rf_gain=71 dB   rx1_rssi: symbol=10925 preamble=11150
  rx_sampling_freq=30720000 Hz   tx_sampling_freq=30720000 Hz