xilinx jesd204c link establishment failed

JTHY on Jun 2, 2026

Category: Hardware

Product Number: ADRV9029

dear teams,

Now I porting ADI’s no-OS project to an HDL project based on Xilinx JESD204C. At present, the JESD204B link has not been established.

configuration of my jesd204c:

fpga jesd204c tx:

Offset address	Register name	Parameter	Actual parameter
0x03C	OFSADDR_CTRL_8B10_CFG	0x03 0B 1F 03	ILA multiframes:4 Enable Link Error counters : 1 Error Reporting via sync : 0 ILA Required: 1 Scrambling:1 Frames per Multiframe (K): 1F(32) Octets per Frame (F):3(4)
0x050	OFSADDR_CTRL_SYSREF	0x01	1 = The core will align the LMFC/LEMC counter on all SYSREF events; no longer configured
0x048	OFSADDR_CTRL_TEST_MODE	0x00	GT loopback: (TX only)00: Normal operation
0x040	OFSADDR_CTRL_LANE_ENA	0x0f
0x034	OFSADDR_CTRL_SUB_CLASS	0x01	1 = Subclass 1
0x074	CTRL_TX_ILA_CFG1	0x00170F07 -> 0x000F0F07	Control bits per Sample:0 N'=16 N=16 M=8
0x078	CTRL_TX_ILA_CFG2	0x00	Control word per Sample:0x0 high density = 0 S=0(1)
0x07C	CTRL_TX_ILA_CFG3	0x00	ADJDIR:0 PHAD:0 ADJCNT:0

fpga jesd024c rx:

Offset address	Register	Parameter	Actual parameter
0x03C	OFSADDR_CTRL_8B10_CFG	0x030B1F03	ILA multiframes:4 Enable Link Error counters : 1 Error Reporting via sync : 0 ILA Required: 1 Scrambling:1 Frames per Multiframe (K): 1F(32) Octets per Frame (F):3(4)
0x050	OFSADDR_CTRL_SYSREF	0x01
0x048	OFSADDR_CTRL_TEST_MODE	0x00
0x034	OFSADDR_CTRL_SUB_CLASS	0x01

adrv9029 framer:

    \"framer\": [ \n\
      { \n\
        \"serializerLaneCrossbar\": { \n\
          \"lane0FramerOutSel\": 0, \n\
          \"lane1FramerOutSel\": 1, \n\
          \"lane2FramerOutSel\": 2, \n\
          \"lane3FramerOutSel\": 3 \n\
        }, \n\
        \"adcCrossbar\": { \n\
          \"conv0\": 1, \n\
          \"conv1\": 0, \n\
          \"conv2\": 3, \n\
          \"conv3\": 2, \n\
          \"conv4\": 5, \n\
          \"conv5\": 4, \n\
          \"conv6\": 7, \n\
          \"conv7\": 6, \n\
          \"conv8\": 127, \n\
          \"conv9\": 127, \n\
          \"conv10\": 127, \n\
          \"conv11\": 127, \n\
          \"conv12\": 127, \n\
          \"conv13\": 127, \n\
          \"conv14\": 127, \n\
          \"conv15\": 127, \n\
          \"conv16\": 127, \n\
          \"conv17\": 127, \n\
          \"conv18\": 127, \n\
          \"conv19\": 127, \n\
          \"conv20\": 127, \n\
          \"conv21\": 127, \n\
          \"conv22\": 127, \n\
          \"conv23\": 127 \n\
        }, \n\
        \"enableJesd204C\": 0, \n\
        \"bankId\": 0, \n\
        \"deviceId\": 1, \n\
        \"lane0Id\": 0, \n\
        \"jesd204M\": 8, \n\
        \"jesd204K\": 32, \n\
        \"jesd204F\": 4, \n\
        \"jesd204Np\": 16, \n\
        \"jesd204E\": 0, \n\
        \"scramble\": 1, \n\
        \"serializerLanesEnabled\": 15, \n\
        \"lmfcOffset\": 0, \n\
        \"syncbInSelect\": 0, \n\
        \"overSample\": 0, \n\
        \"syncbInLvdsMode\": 1, \n\
        \"syncbInLvdsPnInvert\": 1, \n\
        \"newSysrefOnRelink\": 0, \n\
        \"sysrefForStartup\": 0, \n\
        \"sysrefNShotEnable\": 0, \n\
        \"sysrefNShotCount\": 0, \n\
        \"sysrefIgnoreWhenLinked\": 0 \n\
      }, \n\
      
          \"serCfg\": [ \n\
      { \n\
        \"serAmplitude\": 0, \n\
        \"serPreEmphasis\": 0, \n\
        \"serPostEmphasis\": 0, \n\
        \"serInvertLanePolarity\": 1 \n\
      }, \n\
      { \n\
        \"serAmplitude\": 0, \n\
        \"serPreEmphasis\": 0, \n\
        \"serPostEmphasis\": 0, \n\
        \"serInvertLanePolarity\": 1 \n\
      }, \n\
      { \n\
        \"serAmplitude\": 0, \n\
        \"serPreEmphasis\": 0, \n\
        \"serPostEmphasis\": 0, \n\
        \"serInvertLanePolarity\": 1 \n\
      }, \n\
      { \n\
        \"serAmplitude\": 0, \n\
        \"serPreEmphasis\": 0, \n\
        \"serPostEmphasis\": 0, \n\
        \"serInvertLanePolarity\": 1 \n\
      } \n\
    ], \n\

adrv9029 deframer:

    \"deframer\": [ \n\
      { \n\
        \"deserializerLaneCrossbar\": { \n\
          \"deframerInput0LaneSel\": 0, \n\
          \"deframerInput1LaneSel\": 1, \n\
          \"deframerInput2LaneSel\": 2, \n\
          \"deframerInput3LaneSel\": 3 \n\
        }, \n\
        \"enableJesd204C\": 0, \n\
        \"bankId\": 0, \n\
        \"deviceId\": 1, \n\
        \"lane0Id\": 0, \n\
        \"jesd204M\": 8, \n\
        \"jesd204K\": 32, \n\
        \"jesd204F\": 4, \n\
        \"jesd204Np\": 16, \n\
        \"jesd204E\": 0, \n\
        \"scramble\": 1, \n\
        \"deserializerLanesEnabled\": 15, \n\
        \"lmfcOffset\": 0, \n\
        \"syncbOutSelect\": 0, \n\
        \"syncbOutLvdsMode\": 1, \n\
        \"syncbOutLvdsPnInvert\": 0, \n\
        \"syncbOutCmosSlewRate\": 0, \n\
        \"syncbOutCmosDriveLevel\": 0, \n\
        \"dacCrossbar\": { \n\
          \"tx1DacChanI\": 1, \n\
          \"tx1DacChanQ\": 0, \n\
          \"tx2DacChanI\": 3, \n\
          \"tx2DacChanQ\": 2, \n\
          \"tx3DacChanI\": 5, \n\
          \"tx3DacChanQ\": 4, \n\
          \"tx4DacChanI\": 7, \n\
          \"tx4DacChanQ\": 6 \n\
        }, \n\
        \"newSysrefOnRelink\": 0, \n\
        \"sysrefForStartup\": 1, \n\
        \"sysrefNShotEnable\": 0, \n\
        \"sysrefNShotCount\": 0, \n\
        \"sysrefIgnoreWhenLinked\": 0 \n\
      }, \n\
      
          \"desCfg\": [ \n\
      { \n\
        \"highBoost\": 0, \n\
        \"configOption1\": 0, \n\
        \"configOption2\": 0, \n\
        \"configOption3\": 0, \n\
        \"configOption4\": 0, \n\
        \"configOption5\": 0, \n\
        \"configOption6\": 0, \n\
        \"configOption7\": 0, \n\
        \"configOption8\": 0, \n\
        \"configOption9\": 0, \n\
        \"configOption10\": 0, \n\
        \"desInvertLanePolarity\": 0 \n\
      }, \n\
      { \n\
        \"highBoost\": 0, \n\
        \"configOption1\": 0, \n\
        \"configOption2\": 0, \n\
        \"configOption3\": 0, \n\
        \"configOption4\": 0, \n\
        \"configOption5\": 0, \n\
        \"configOption6\": 0, \n\
        \"configOption7\": 0, \n\
        \"configOption8\": 0, \n\
        \"configOption9\": 0, \n\
        \"configOption10\": 0, \n\
        \"desInvertLanePolarity\": 1 \n\
      }, \n\
      { \n\
        \"highBoost\": 0, \n\
        \"configOption1\": 0, \n\
        \"configOption2\": 0, \n\
        \"configOption3\": 0, \n\
        \"configOption4\": 0, \n\
        \"configOption5\": 0, \n\
        \"configOption6\": 0, \n\
        \"configOption7\": 0, \n\
        \"configOption8\": 0, \n\
        \"configOption9\": 0, \n\
        \"configOption10\": 0, \n\
        \"desInvertLanePolarity\": 0 \n\
      }, \n\
      { \n\
        \"highBoost\": 0, \n\
        \"configOption1\": 0, \n\
        \"configOption2\": 0, \n\
        \"configOption3\": 0, \n\
        \"configOption4\": 0, \n\
        \"configOption5\": 0, \n\
        \"configOption6\": 0, \n\
        \"configOption7\": 0, \n\
        \"configOption8\": 0, \n\
        \"configOption9\": 0, \n\
        \"configOption10\": 0, \n\
        \"desInvertLanePolarity\": 1 \n\
      } \n\
    ], \n\

Debuging result：

TX DAC Link (FPGA TX FRAMER -> ADRV9029 TX DEFRAMER)：

Data captured by FPGA ILA:

data	-
tx_sync	1
rx_reset_done	1

FPGA TX_STAT_STATUS: 0x1002(SYSREF captured)

bit	value	description
15	1	8b10b 1= 8b10b rx misalignment has been detected.
14	0	8b10b 1= the link has started outputting data on the axi-stream port
13	0	8b10b 1 = The link has achieved Code Group Sync
12	0	8b10b 1 = The receiver has signaled SYNC has been achieved.
10	0	1 = The receiver buffer has overflowed.
5	0	64B66B
4	0	64B66B
2	0	SYSREF error
1	1	SYSREF captured
0	0	Interrupt pending

adi_adrv9025_DeframerStatusGet() returned data: 0x12 (FS LOST, frame synchronization lost, sysref received; the correct value should be 0x87)

status bit	value	description
7	0	Valid checksum
6	0	EOF Event
5	0	EOMF Event
4	1	FS lost; frame synchronization
3	0	user data valid
2	0	reserved
1	1	sysref received
0	0	sync_level

RX ADC Link (ADRV9029 ADC FRAMER -> FPGA RX DEFRAMER)

Data captured by FPGA ILA:

rx_sync	0
data	-
rx_reset_done	1

FPGA RX_STAT_STATUS:0x2 (SYSREF capturedd)

bit	value	description
15	0	8b10b 1= 8b10b rx misalignment has been detected.
14	0	8b10b 1= the link has started outputting data on the axi-stream port
13	0	8b10b 1 = The link has achieved Code Group Sync
12	0	8b10b 1 = The receiver has signaled SYNC has been achieved.
10	0	1 = The receiver buffer has overflowed.
5	0	64B66B
4	0	64B66B
2	0	SYSREF error
1	1	SYSREF captured
0	0	Interrupt pending

adi_adrv9025_FramerStatusGet() returned data: 0x0A (SYNCIN LEVEL 1, SYSREF phase established by framer; the correct value should be 0x0A)

status bit	value	description
7	0	reserved
6	0	reserved
5	0	reserved
4	0	reserved
3	1	SYNCIN LEVEL(1 high 0 low)
2	0	SYSREF phase error
1	1	SYSREF phase established by framer
0	0	Configuration error: 1

my hdl prj(vivado2025.1):drive.google.com/.../view

my noos prj and cfg file：https://drive.google.com/file/d/1QK4T439lnm6Kb3SLwF1wWA0J9sXEjrMb/view?usp=drive_link

Where should I start troubleshooting this issue?

best regards，

zjy

Thread Notes

hardware zcu102 noos ADRV9029 software defined radio rf and microwave Adrv9029 Eval Show More

TudorG

on Jun 3, 2026 6:23 AM
0
Hello,

We cannot access the folders provided as they require permission. Can you provide access so we can look over the code?

Regards,

Tudor
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JTHY on Jun 3, 2026 12:55 PM in reply to TudorG
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Hi TudorG,

I’m very sorry. I have now updated the sharing settings and made the link accessible to everyone. You should be able to download it now.

best regards，

jthy
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TudorG

on Jun 4, 2026 5:41 AM in reply to JTHY
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Thank you, we'll look into it and get back to you with an answer.
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Thread Details

xilinx jesd204c link establishment failed

TX DAC Link (FPGA TX FRAMER -> ADRV9029 TX DEFRAMER)：

RX ADC Link (ADRV9029 ADC FRAMER -> FPGA RX DEFRAMER)

Thread Notes