We're evaluating the AD8093 for a new design, so we attached the AD9083EBZ to our custom board (i.o.w. not the zcu102). The MPSoC is also a ZU9.
I've ported the reference design for the zcu102 to our system, and that now works and produces data.
There's one problem however. The reference design obtains a 500 MHz clock (ref_clk0) from the clock chip and uses this to clock some of the JESD blocks. Our ZU9 is only speedgrade "-1" whereas the zcu102 board has a faster "-2" speedgrade. The 500 MHz clock is not supported on the -1 devices, and leads to timing errors.
So far I've just waived the timing failures and got lucky as the design appears to work fine.
I do want to keep the 125MHz sampling rate. The transceivers are fine at 12.5 Gbps.
How do I got about changing this particular reference clock?