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AD9083 on speed grade -1

Thread Summary

The user encountered timing errors when using a 500 MHz reference clock (ref_clk0) with a ZU9 -1 speedgrade device in a custom board design for the AD9083. The solution involves changing the ref_clk0 to 250 MHz and adjusting the QPLL parameters accordingly. The user should also update the device tree to use the DIV1 output of the PHY for generating the link clk and set the lane rate to 10 Gbps. Analog Devices has updated the project to support these changes and provided a user guide for generating the necessary PHY parameters.
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Category: Software
Product Number: AD9083

We're evaluating the AD8093 for a new design, so we attached the AD9083EBZ to our custom board (i.o.w. not the zcu102). The MPSoC is also a ZU9.

I've ported the reference design for the zcu102 to our system, and that now works and produces data.

There's one problem however. The reference design obtains a 500 MHz clock (ref_clk0) from the clock chip and uses this to clock some of the JESD blocks. Our ZU9 is only speedgrade "-1" whereas the zcu102 board has a faster "-2" speedgrade. The 500 MHz clock is not supported on the -1 devices, and leads to timing errors.

So far I've just waived the timing failures and got lucky as the design appears to work fine.

I do want to keep the 125MHz sampling rate. The transceivers are fine at 12.5 Gbps.

How do I got about changing this particular reference clock?

  • Hi  

    We're looking into it and will come back with an answer as soon as possible.

    Thank you for your patience.


    Best regards,
    Robert

  • Thanks in advance.

    What I've found so far is that it appears that the 500MHz clock only routes to the QPLL/CPLL inputs of the GTH. It should be okay to run the clock at 250 instead and set the QPLL parameters accordingly to generate the 12.5GT/s configuration. The IP configuration items for the JESD PHY are rather cryptic though.

  • Hi  

    You are right, changing the refclk value to 250MHz is the right approach. The key parameters you need to change in the JESD PHY are presented in the GTH user guide page 48-49 and also 158 and 217.

    You need to also make sure to change the refclk in the device tree and to use the DIV1 output of the PHY instead of the DIV2 for generating the link clk and you do it by changing this to <XCVR_REFCLK>.

    As a side note the real Lane rate of our default profile is 10Gbps, not 12.5Gbps (lane_rate = linkclk * 40, where linkclk is 250MHz). If you got the 12.5Gbps value from the jesd PHY IP, and not by using a different JESD configuration, you can just ignore that parameter or change it to 10 instead.

    Best regards,
    Andrei

  • I'll delve into this. I got the 12.5 from the IP, so it's not true then.

    As the transceivers on the AD9083 can go up to 16 GT/s, does that mean I could transfer close to 200 MS/s? Or is the 125MHz an internal limit?

  • Hi  ,

    We are currently working on a version with 15Gbps, Np=12 and IQ sample rate = 250MHz by applying this formula. Also link_clk=375MHz and device_clk=250MHz and total decimation = 8 in order to get 2GSPS ADC rate. This configuration seems to work on the VCU118 from what we've tested and in theory it should also work on ZCU102.

    Best regards,
    Andrei

  • If I open the JESD PHY configuration, I get lots of cryptic "raw" register values. I suspect Qpll Fbdiv which is now "0000101000" (=40) needs to be doubled to 80 then. The GTH user guide isn't very helpful as it says to "Use the recommended value from the Wizard." for any register that appears to match the table.

    Or is there another way to configure the PHY that I'm missing here?

  • Hi  ,

    Here's our user guide. You can use the scripts that are described here to generate the parameters for your configuration then you just copy them into the PHY.

    Best regards,
    Andrei

  • Helps, but I can't match those descriptions with what I see in the reference design for the ad9083. Looks like it's using none of the three methods?

    In 'system.tcl' it just contains the raw register set and apparently none of the generators are actually being used for the ad9083 design:

    # Create instance: util_ad9083_xcvr, and set properties
    set util_ad9083_xcvr [ create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_ad9083_xcvr ]
    set_property -dict [list \
    CONFIG.CH_HSPMUX {0x2424} \
    CONFIG.POR_CFG {0x0000} \
    CONFIG.PREIQ_FREQ_BST {0} \
    CONFIG.QPLL_CFG0 {0x391c} \
    CONFIG.QPLL_CFG1 {0x0000} \
    CONFIG.QPLL_CFG1_G3 {0x0020} \
    CONFIG.QPLL_CFG2 {0x0f80} \
    CONFIG.QPLL_CFG2_G3 {0x0f80} \

    and so on.

  • Also interesting, I tried re-building the zcu102 reference design from scratch, but it won't build on current "main" branch, I get this now:

    :~/projects/adihdl/projects/ad9083_evb/zcu102$ make
    make[2]: *** [Makefile:33: if_framelock.xml] Error 127
    make[1]: *** [../scripts/library.mk:134: interfaces/if_framelock.xml] Error 2
    make: *** [../../scripts/project-xilinx.mk:141: ../../../library/axi_dmac/component.xml] Error 2

    Update: Appears to be related to not having sourced the Vivado scripts. Ran it in the wrong shell.

  • Hi  ,

    We've just updated the project of the main branch to automatically add the correct PHY parameters + the new 15Gbps use case that I mentioned before. The other method that was presented in our guide was to use the gtwizard_generator.tcl script in order to generate your configuration, then gtwiz_parser.pl to create a text file containing the correct parameters and values that needed to be changed in the PHY, but you needed to change them manually. With this new support you no longer have to do that.

    Best regards,
    Andrei

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