Hello,
I tried to build the VCK190 reference design for the AD9081 with custom parameters.
The command used:
make JESD_MODE=8B10B REF_CLK_RATE=122.88 RX_JESD_L=2 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 RX_LANE_RATE=4.9152 TX_JESD_L=2 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 TX_LANE_RATE=4.9152
Building the design with this command failes in board validation, as the configuration of the versal gt_quad ip does not seem to be correct. While there should be only two lanes enabled, all four are enabled - which makes the validation fail, as lane2 and lane3 do not have a valid clock connected. Also the configuration of the quad ip seems to be based on the JESD204_64B66B preset instead of the JESD204_8B10B.
The Problem seems to be only in ad9081_fmca_ebz/common/versal_transceiver.tcl - For example the JESD_MODE preset is hardcoded (line 220)
set preset ${transceiver}-JESD204_64B66B
Can your reference design support JESD204_8B10B if i change that line or are there other parameters relating to the JESD MODE that i would have to configure manually?
The problem in validation can be resolved by adding the following lines (~line 790, else to if($asymmetric_mode))
} else {
set_property -dict [list \
CONFIG.PROT0_NO_OF_LANES.VALUE_MODE MANUAL \
CONFIG.PROT0_NO_OF_LANES [expr max($quad_num_rx_lane, $quad_num_tx_lane)] \
] [get_bd_cells ${ip_name}/gt_quad_base_${j}]
}
With those changes it can successfully generate an Image. When testing on the Board i could not get it to work yet.
On boot i get those messages:
when using "jesd204-ignore-errors;" i get this from jesd_status:
