Hi everyone,
I am working with an Alinx AX7350B + ADRV9002 platform.
I have successfully ported the zc706-adrv9002 design and integrated it with my srsRAN LTE project. At the moment, the IQ data is transferred between the host and the board through the PS Ethernet interface.
With this setup, I can operate successfully at:
- 1.4 MHz
- 3 MHz
- 5 MHz
and I can observe the LTE spectrum correctly.
However, when I try:
- 10 MHz SISO, or
- 5 MHz MIMO 2x2
I hit a clear limitation on the Zynq PS side. The Linux system reports errors such as:
sched: RT throttling activated
From my debugging, it seems the main issue is CPU load / packet processing overhead on the PS side, rather than the RF chain itself.
So now I would like to move to a different architecture and use PL Ethernet so that the sample path can avoid the PS as much as possible.
My target idea is something like:
Host -> Ethernet -> PL packet processing / DMA -> ADRV9002
and similarly for the RX path.
My questions are:
- Is there any existing ADI / Vivado reference design or example that is close to this type of architecture, especially for ADRV9002 or similar ADI transceivers?
- For a PL-Ethernet-based approach, what is the recommended data path?
- Should the Ethernet packets be parsed in PL and the IQ payload sent directly toward the RF DMA path?
- Or is it better to go first through DDR using AXI DMA and then stream to the ADRV9002?
- Has anyone tried combining PL Ethernet with an ADI transceiver HDL design to bypass the PS bottleneck for high-rate host streaming?
Any advice or pointers would be very appreciated.
Thanks.
