Category: Software
Product Number: AD9083
I'm building a design using the AD9083. I built the reference design for the EVM and now want to move that to our custom board.
When I add my custom RTL code to the project, I get this message from Vivado 2025.1:
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI' of definition 'analog.com:interface:if_xcvr_cm:1.0' (from User Repositories).
Apparently it now sees the standard AXI LITE interface from my RTL code as some custom ADI bus. As a result, it won't connect it to the AXI smartconnect or interconnect. How do I prevent this from happening?
The port definition of my RTL looks like this:
-- Miscellaneous
adc_active : out std_logic;
data_sync_start : in std_logic;
data_enable : in std_logic;
-- ADC input interface
adc_dat_a : in std_logic_vector(c_adc_dwidth - 1 downto 0);
adc_dat_b : in std_logic_vector(c_adc_dwidth - 1 downto 0);
-- AXI4-Stream output interface
aclk : in std_logic; -- sample clock and streaming clock
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_tdata : out std_logic_vector(c_axis_dwidth - 1 downto 0);
-- AXI lite register interface
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWPROT : in std_logic_vector(2 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_AWREADY : out std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARPROT : in std_logic_vector(2 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_RREADY : in std_logic
