Category: Software
Product Number: AD9361
Software Version: HDL Reference Design
I am seeing a Hold Time Violation (WHS) when using the latest ADI reference HDL for the AD9361 on both ZC702 and ZC706. Despite using default strategies and attempting Performance-based strategies, the design consistently fails timing in the rx_clk domain.
Environment:
- Tool Version: Vivado v.2025.1 (win64)
- Device: FMCOMMS2
- Reference Design: HDL_Main Branch
- Carrier/Board: ZC702 (and ZC706)
Timing Summary Highlights:
- WNS: 0.136 ns (Met)
- WHS: -0.173 ns (FAILED)
- Failing Domain: rx_clk (250 MHz)
- Total Hold Slack (THS): -1.241 ns
- Total Failing Endpoints: 17
Key Observations from Report:
- Clock Skew: High negative skew (~ -0.335ns) between the source clock delay (3.190ns) and destination clock delay (2.740ns) on the clk_fpga_0 to rx_clk boundaries.
- Critical Warnings: 7 occurrences of TIMING-54 (Scoped false path/clock group constraints ignored).
- Methodology Warnings: CKBF-1 (BUFR driver warnings) and PDRC-190 (Suboptimally placed synchronizer chains).
