Hello
My customer had made ES, and they are evaluating the set using AD4080.
They use x4 AD4080( and ADA4945 ,LTC6655) for 1unit.
Interface is,SPI interface/ FIFO enabled/ Quad data-lane is used.( NOT LVDS)
Here is customers 3 questions.
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Q1). FIFO READ DONE flag
Much more serious problem exists and I would like your advice to work around.
The FIFO READ DONE flag is correctly set when the FIFO is in (1) immediate triggerLTC6655)
or (2) event trigger read latest watermark.
However, the READ DONE is **never** set in the (3) event trigger read all FIFO mode.
The real behaviour is different from the table 27 of the datasheet (rev B).
This makes it impossible to implement a pre-triggered capture. Any work around?
Q2). Chip revision from marking
Is there a way to know the revision of the chip in my hand?
Given these many discrepancies from the document, I suspect my device in hand may be too old.
Q3) FIFO Full
Your Question about FIFO Full(*),If thre were mis-understanding, please let me know.
Your comment
For Q1 please clarify; the expected behavior is as shown in figs. 87 and figs.88 The FIFO will be asserted when the watermark is reached, its is cleared when the first result is read and is expected to remain cleared until the FIFO is re-triggered and filled. FIFO_READ_DONE will be asserted when all the results have been read from the FIFO. Is this the behavior being observed?
(*)
ez.analog.com/.../fifo-full-signal
Ans. From Customer
1. Clarification to the FIFO full signal question.
Let me clarify. As you mentioned, the FIFO_FULL flag is supposed to be cleared when the first data is read.
However, it is kept asserted even after the first data is read. The FULL flag is cleared when the
FIFO is disabled vai the general configuration register.
If thre were mis-understanding, please let me know.
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Thank you for your support!,
But please advise soon because they need to study pre-production sson.
Sorry to bother you,
Best Regards
