Hello!
The combination of the Data Offload Engine and util_hbm ip cores is supposed to be capable of handling 8GB of external DRAM, but after migrating our design from ZCU102 to a new custom PCB with more RAM Resources (8GB) the synthesis of util_hbm fails with the following errors:
When looking into this i found, that ADDR_OFFSET is a local parameter (in util_hbm.v), which in Verilog means 32-bit integer. Since the address width of the axi interface is 33 for 8GB this seems to be the reason for the synthesis failing.
localparam ADDR_OFFSET = (MEM_TYPE == 1) ? DDR_BASE_ADDDRESS :
(HBM_SEGMENT_INDEX+i) * HBM_SEGMENTS_PER_MASTER * 256 * 1024 * 1024 ;
(line 262-263, util_hbm.v)
The 32 bit localparam is accessed later like this:
.req_dest_address(ADDR_OFFSET[AXI_ADDR_WIDTH-1:AXI_BYTES_PER_BEAT_WIDTH]),
after the following changes the synthesis finishes successfully.
localparam [AXI_ADDR_WIDTH-1:0] ADDR_OFFSET = (MEM_TYPE == 1) ? DDR_BASE_ADDDRESS :
(HBM_SEGMENT_INDEX+i) * HBM_SEGMENTS_PER_MASTER * 256 * 1024 * 1024 ;
so my question is: is this a bug or have we made a mistake in our configuration and it should work without this modification?
