Category: Hardware
Product Number: FPGA
Hello,
We are having some trouble with the tx path using a JESD204B link with AD9371 and FPGA (error 0x61). We have been probing a bit on the FPGA with ILA-cores and have found that the ILAS_config_data, ILAS_config_rd, and ILAS_config_addr is behaving weird during the error - no data is being set.
So, what determines how up_wreq and up_cfg_is_writeable behaves? ie. when is it allowed to set the data?
I have posted below some code and waveforms:
always @(posedge up_clk) begin
if (up_reset == 1'b1) begin
up_cfg_ilas_data_did <= 'h00;
up_cfg_ilas_data_bid <= 'h00;
up_cfg_ilas_data_scr <= 'h00;
up_cfg_ilas_data_f <= 'h00;
up_cfg_ilas_data_k <= 'h00;
up_cfg_ilas_data_m <= 'h00;
up_cfg_ilas_data_n <= 'h00;
up_cfg_ilas_data_cs <= 'h00;
up_cfg_ilas_data_np <= 'h00;
up_cfg_ilas_data_subclassv <= 'h00;
up_cfg_ilas_data_s <= 'h00;
up_cfg_ilas_data_jesdv <= 'h00;
up_cfg_ilas_data_cf <= 'h00;
up_cfg_ilas_data_hd <= 'h00;
up_cfg_ilas_data_l <= 'h00;
for (i = 0; i < NUM_LANES; i = i + 1) begin
up_cfg_ilas_data_lid[i] <= 'h00;
up_cfg_ilas_data_fchk[i] <= 'h00;
end
end else if (up_wreq == 1'b1 && up_cfg_is_writeable == 1'b1) begin
for (i = 0; i < NUM_LANES; i = i + 1) begin
if (up_waddr[10:2] == ('h310 / 16) + i*2) begin
case (up_waddr[1:0])
2'h0: begin
up_cfg_ilas_data_bid <= up_wdata[27:24];
up_cfg_ilas_data_did <= up_wdata[23:16];
end
2'h1: begin
up_cfg_ilas_data_k <= up_wdata[28:24];
up_cfg_ilas_data_f <= up_wdata[23:16];
up_cfg_ilas_data_scr <= up_wdata[15];
up_cfg_ilas_data_l <= up_wdata[12:8];
up_cfg_ilas_data_lid[i] <= up_wdata[4:0];
end
2'h2: begin
up_cfg_ilas_data_jesdv <= up_wdata[31:29];
up_cfg_ilas_data_s <= up_wdata[28:24];
up_cfg_ilas_data_subclassv <= up_wdata[23:21];
up_cfg_ilas_data_np <= up_wdata[20:16];
up_cfg_ilas_data_cs <= up_wdata[15:14];
up_cfg_ilas_data_n <= up_wdata[12:8];
up_cfg_ilas_data_m <= up_wdata[7:0];
end
2'h3: begin
up_cfg_ilas_data_fchk[i] <= up_wdata[31:24];
up_cfg_ilas_data_hd <= up_wdata[7];
up_cfg_ilas_data_cf <= up_wdata[4:0];
end
endcase
end
end
end
Here is a waveform of a successful init:
Here is a failing init:
Thanks in advance
