Xilinx JESD204 PHY

Hello 1112luke ,

Yes, the IP you referenced can be used as a replacement for util_adxcvr within the ADI JESD204 RX chain.

We also have an example where we used a different Physical Layer for the quad‑MXFE. Specifically, it is the JESD204‑PHY IP from Xilinx, which is compatible with GTH4.

The documentation is available here:

https://docs.amd.com/r/en-US/pg198-jesd204-phy/JESD204-PHY-v4.1-LogiCORE-IP-Product-Guide 

As a reference, you may review the quad‑MXFE design, where this IP is used. 

The relevant portion of the block design script can be found here:

https://github.com/analogdevicesinc/hdl/blob/main/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl#L154-L191 

If you have further questions or require additional clarification, please continue the discussion within this thread (Xilinx JESD204 PHY - Q&A - FPGA Reference Designs - EngineerZone), without opening a new one, so that we can maintain all context and details in a single place.

Best regards,

Maria

Hello 1112luke ,

Yes, the IP you referenced can be used as a replacement for util_adxcvr within the ADI JESD204 RX chain.

We also have an example where we used a different Physical Layer for the quad‑MXFE. Specifically, it is the JESD204‑PHY IP from Xilinx, which is compatible with GTH4.

The documentation is available here:

https://docs.amd.com/r/en-US/pg198-jesd204-phy/JESD204-PHY-v4.1-LogiCORE-IP-Product-Guide 

As a reference, you may review the quad‑MXFE design, where this IP is used. 

The relevant portion of the block design script can be found here:

https://github.com/analogdevicesinc/hdl/blob/main/projects/ad_quadmxfe1_ebz/common/ad_quadmxfe1_ebz_bd.tcl#L154-L191 

If you have further questions or require additional clarification, please continue the discussion within this thread (Xilinx JESD204 PHY - Q&A - FPGA Reference Designs - EngineerZone), without opening a new one, so that we can maintain all context and details in a single place.

Best regards,

Maria