Hiandrei_g ,
For my earlier thread,
https://ez.analog.com/fpga/f/q-a/601964/issue-connecting-custom-cw-generator-to-dac-fifo-in-adrv9364z7020-reference-design
Based on the guidance provided there, I attempted to change the DAC_DDS_SEL mux setting to route DMA data to the DAC output. However, I am facing some issues and would appreciate your support.
From the Address Editor, the base address for the DAC core (axi_ad9361) is:
-
Base Address:
0x7902_0000
To control the DAC_DDS_SEL mux for Channel-0, I used the following calculation:
-
IP Base Address:
0x7902_0000 -
Register Offset (CHAN_CNTRLn_7):
0x0418 -
Final Address:
0x7902_0418
For the remaining channels, I used the formula:
address = 0x79020000 + 0x418 + (n * 0x40)Using this formula, I calculated the addresses for all channels and wrote the value 0x2 (to select DMA input data) using devmem in order to route DMA data to the DAC.
However, I am still unable to observe my custom CW signal (implemented in HDL) at the DAC output. Additionally, from around the third channel onward, it seems that register writes are not taking effect. When I read back the register values for those channels, the value returned is 0xDEADDEAD (screenshot attached).
I have the following questions:
-
What is the correct configuration sequence to route DMA data to the DAC?
-
Why am I seeing
0xDEADDEADwhen reading some channel register addresses?
Does this indicate an invalid or unmapped address region,?
Could you please help clarify the correct configuration procedure and the reason for this behavior?
