Change Hdl design clk rates

Hello VICKY1 ,

Do you have any updates? Do you still need assistance on this issue?

Best regards,

Maria

Thanks for the repy
i think still they didnt talked about how to change bandwidth clk rates in the links

The interface core clock 30.72 MHz is resulted from the sampling rate and interface cmonfig. Changing the sampling rate changes the clock you want. To change the sampling rate you need to upload a profile.
I gave you links on info regarding profile generation above.
Have you tried to load a profile?

The interface clock frequency depends on interface type (LVDS/CMOS) and more. See the core info for more details AXI ADRV9001 — HDL documentation.

Andrei

The interface core clock 30.72 MHz is resulted from the sampling rate and interface cmonfig. Changing the sampling rate changes the clock you want. To change the sampling rate you need to upload a profile.
I gave you links on info regarding profile generation above.
Have you tried to load a profile?

The interface clock frequency depends on interface type (LVDS/CMOS) and more. See the core info for more details AXI ADRV9001 — HDL documentation.

Andrei