Porting Reference Design to VCK190

Hello Taka314 ,

I moved your thread to the FPGA Reference Designs  group for better assistance regarding the HDL porting issues.

Could you provide us more details about:

• the HDL branch/release you started with
• the files you changed & the modifications you applied
• if you updated the constraints files according to the vck190 schematic
• what issues did you exactly encounter

Kind regards,

Stanca

VCK190 electrically cannot support the ADRV9009's eval board. The VDD_INTERFACE needed is 1.71 V min. Versal boards only provide 1.5 V max.

-Travis

Hi, we did try this in the past and it wasn't reliable. ADRV9009 needs 1.7V minimum and Versal's maximum is 1.5V.

Hey yes Im trying to build a VCK190 example because after we want to port it over to a custom board (Iwave G57M VE2302 platform) Which I know is able to provide the necessary voltage. I started with the https://github.com/analogdevicesinc/hdl/tree/main/projects/adrv9009/zcu102 and then attempted to switch out the transciever generator tool for the versal one but that kept resulting in error after error. I was wondering if anyone has tried it and was able to get a successful platform build working.  

Hi! We do have some examples for the VCK190, but it won't work properly with the adrv9009 from our experience.

You can find some example projects that use the Versal transceiver here:

- https://github.com/analogdevicesinc/hdl/tree/main/projects/ad9081_fmca_ebz/vck190

- https://github.com/analogdevicesinc/hdl/tree/main/projects/ad9084_ebz/vck190

Regards,

Bogdan