AD9144 Xilinx JESD204 PHY IP Issues

We have a customer experiencing repeated PRBS test failures on all eight JESD lanes between an AD9144 DAC (on the AD9144‑FMC‑EBZ board) and a Xilinx FPGA running a JESD204 PHY and JESD204C TX endpoint at 2.5 Gbps with 8b/10b encoding. Although both the DAC and SERDES PLLs report being locked and the Xilinx PHY is configured to transmit PRBS7 as instructed in the AD9144 datasheet, the DAC’s PHY PRBS status register (0x31D) indicates a failure, with non‑zero total and per‑lane error counts. The customer verified that deliberate PRBS pattern mismatches cause expected threshold‑level errors, but when both ends are set to PRBS7, the resulting error counts are still low but non‑zero—insufficient for a passing result. 

We found a somehow related issue from 9 years ago that might be helpful (AD9144 PHY PRBS15, Datapath PRBS7 and PRBS15) but the Github links in the thread couldn't be opened (maybe they were moved to a different

branch?). Could you please provide access to these links? 

Best regards,
Marco