I am experiencing a **SPI1 clock configuration failure** on my ZCU102 Rev D1 board that prevents **all** FMC cards from working. Both ADRV9009-W/PCBZ and FMCOMMS4 (AD9364) fail with SPI communication errors. The root cause appears to be:
```
zynqmp_clk_divider_set_rate() set divider failed for spi1_ref_div1, ret = -13
```
This error occurs at boot time before any device-specific driver loads, causing SPI1 to malfunction while SPI0 (QSPI flash) works perfectly.
---
## Hardware Configuration
- **Carrier Board:** Xilinx ZCU102 Rev D1
- **FMC Cards Tested:**
- ADRV9009-W/PCBZ (on HPC0)
- FMCOMMS4 / AD9364 (on HPC0)
- **Software:** ADI Kuiper Linux (tested 2021 and latest images)
- **Boot Mode:** SD Card
---
## The Problem
### Error Message (appears on EVERY boot):
```
[ 3.645235] zynqmp_clk_divider_set_rate() set divider failed for spi1_ref_div1, ret = -13
```
Error -13 is `EACCES` (Permission denied), indicating the PMU firmware is rejecting the clock divider configuration request.
### Result with ADRV9009:
```
[ 12.199560] iio iio:device1: SPI Read Verify failed (0xFFFFFF)
[ 12.205424] ad9528 spi1.0: Dropping the link to regulator.0
[ 12.211068] ad9528: probe of spi1.0 failed with error -5
```
### Result with FMCOMMS4 (AD9364):
```
[ 7.941805] ad9361 spi1.0: ad9361_probe : Unsupported PRODUCT_ID 0xFF
```
Both cards return **0xFF/0xFFFFFF** on SPI reads, indicating the MISO line is stuck high (no response from devices).
---
## Key Finding: SPI0 Works, SPI1 Fails
| Interface | Device | Result |
|-----------|--------|--------|
| SPI0 | QSPI Flash (m25p80) | 
**Works perfectly** |
| SPI1 | ADRV9009 AD9528 | 
Returns 0xFFFFFF |
| SPI1 | FMCOMMS4 AD9364 | Returns 0xFF |
| I2C | FMC EEPROM | Works |
| I2C | AD7291 (ADRV9009) | Works |
**This proves the FMC connector and cards are fine - only SPI1 is broken.**
---
## Testing Performed
### 1. Multiple FMC Cards
- ADRV9009-W/PCBZ → SPI1 fails
- FMCOMMS4 → SPI1 fails
- Both cards' I2C devices work fine
### 2. Multiple BOOT.BIN Files
- ADRV9009 BOOT.BIN (15.3 MB) → Same SPI1 clock error
- FMCOMMS4 BOOT.BIN (9.9 MB) → Same SPI1 clock error
### 3. Multiple Kuiper Linux Versions
- 2021 Kuiper image → SPI1 clock error
- Latest Kuiper image → SPI1 clock error
### 4. ZCU102 Rev D1 VADJ Fix
- Applied I2C commands to enable VADJ 1.8V
- VADJ confirmed at 1798mV
- DS15 LED is GREEN
- **SPI1 still fails**
---
## Clock Status Analysis
```bash
root@analog:~# cat /sys/kernel/debug/clk/clk_summary | grep -i spi
spi1_ref_mux 0 0 0 <-- enable_count = 0 (NOT ENABLED)
spi1_ref_div1 0 0 0
spi1_ref 0 0 0
qspi_ref_mux 1 1 1 <-- enable_count = 1 (ENABLED)
qspi_ref_div1 1 1 1
qspi_ref 1 1 1
```
The **qspi_ref** clock (SPI0) has enable_count = 1 and works.
The **spi1_ref** clock has enable_count = 0 - it never got enabled due to the divider failure!
---
## PMU Firmware Version
```
zynqmp_firmware_probe Platform Management API v1.1
```
From BOOT.BIN strings:
```
v2.0(release):xilinx-v2019.2
```
---
## Board Details
- **ZCU102 Revision:** Rev D1 (older board, unused for extended period)
- **Known Rev D1 Issue:** VADJ defaults to 0V (already worked around via I2C)
- **Suspected Issue:** PMU firmware incompatibility or corruption
---
## What I've Ruled Out
| Potential Cause | Status |
|-----------------|--------|
| ADRV9009 card defective | Ruled out - FMCOMMS4 also fails |
| FMCOMMS4 card defective | Ruled out - ADRV9009 also fails |
| FMC connector issue | Ruled out - I2C works on both cards |
| Wrong BOOT.BIN | Ruled out - Multiple tested, same error |
| Wrong Kuiper image | Ruled out - Multiple versions tested |
| VADJ power issue | Ruled out - 1.8V verified |
| Software/driver issue | Ruled out - Clock error is in PMU/kernel |
---
## Questions for ADI/Xilinx Community
1. **Is this a known ZCU102 Rev D1 issue?** Similar to the VADJ bug that requires I2C workaround?
2. **Can the SPI1 clock be enabled manually?** Is there a workaround like the VADJ fix?
3. **Does the ZCU102 need a PMU firmware update?** If so, what is the procedure for updating the onboard QSPI firmware?
4. **Is error -13 (EACCES) from PMU normal?** What would cause the PMU to reject a clock divider request?
5. **Has anyone else experienced this?** Especially with older ZCU102 boards that sat unused?
---
## Technical Details
### GPIO Status (Reset lines are correct):
```
gpio-137: AD9528 reset - direction: out, value: 1 (de-asserted)
```
### FMC EEPROM Readable (proves FMC connection is good):
```
root@analog:~# cat /sys/bus/i2c/devices/16-0050/eeprom | hexdump -C | head -5
00000000 01 00 00 01 00 0e 00 f0 01 0d 19 e5 e7 da 8b a1
...
```
### SPI Devices Present:
```
root@analog:~# ls /sys/bus/spi/devices/
spi0.0 spi1.0 spi1.1
```
---
## Summary
This is **not an FMC card issue** - it's a **ZCU102 SPI1 clock configuration failure** that affects all FMC cards. The PMU firmware (error -13) is rejecting the SPI1 clock divider setup, causing SPI1 to be non-functional while SPI0 works fine.
I suspect this may be related to:
- Old/incompatible PMU firmware on the ZCU102's onboard QSPI
- A ZCU102 Rev D1 specific bug (like the VADJ issue)
- Possible corruption from the board sitting unused
Any guidance on updating the ZCU102's onboard firmware or working around this SPI1 clock issue would be greatly appreciated.
---
