Data Offload bypass mode and ddr mode usage issues

Hi nmutech! We are currently looking into your issue. Thanks for understanding!

Hi Cristianmihaipopa1601 , Thanks a lot, I am looking forward to hearing from you. DDR4 usage in data offload with AD9172_fmc_ebz and zcu102 is crucial for us.

Hi,

In a typical reference design, there are 2 attributes you should consider: the bandwidth between the DMA and the memory, respectively the bandwidth between the device and the FPGA. If the bandwidth DMA-memory is less than the bandwidth device-FPGA, then the Data Offload is needed to accommodate this mismatch.

Sometimes in our designs, the user might choose to do a dynamic reconfiguration. This can be done by either lowering the data rate on the device-FPGA side, or choosing to capture a fraction of the available channels (for instance 1/2 channels). This path transitioned from a higher rate to a lower rate, as described in the documentation, resulting in a higher data rate on the DMA-memory path than the device-FPGA path. When this happens, the Data Offload can enter in its bypass setting, in order to just forward the data stream from one domain to the other. So, to conclude, you should use the bypass feature when the actual data rate DMA-mem > actual data rate device-FPGA.

As for the second part of your question, why did you choose to use the external DDR4 storage for the data offload instead of the PS DDR storage? In our reference designs, we typically use the PS DDR memory for the data offload storage for the zcu102 carrier.

Hi IonutP , first let me explain what I’m trying to achieve.

On the software side, I’m trying to load as many samples as possible and generate the longest continuous output from the AD9172. I’m currently using the axi_dac_load_custom_data function, and at the moment I can load 131,072 samples of 32-bit data per sample (16-bit I + 16-bit Q).

The limitation I’m hitting is on the ZCU102, where the maximum offload buffer I can use is:

set dac_offload_size [expr 256*2048] → 512 kB

So effectively I only have 512 kB (~4 Mbit) available for the DAC offload path. With 32-bit IQ samples, that capacity corresponds to about 131,072 samples, which matches what I observe.

When I try to exceed this size, I stop getting valid output on the spectrum analyzer. This gives me roughly 50 µs of waveform duration, because I’m running the AD9172 in Mode 10.

I understand that the ZCU102 has 4 GB PS DDR and 512 MB PL DDR. In theory, if we could use the full PS DDR, we could store up to 32 Gbit of waveform data; and with PL DDR, up to 4 Gbit. However, since we are constrained by the offload buffer size, we are effectively limited to only 512 kB, which prevents us from generating longer waveforms.

For reference, the bit-rate / duration calculations and the reasoning behind the achievable waveform length are discussed in this thread:
https://ez.analog.com/fpga/f/q-a/597844/util_dacfifo-bypass-mode-speed

Unfortunately, 50 µs is not sufficient for our application. If we could bypass the current dac_offload limitation and stream data from PS DDR, we could theoretically generate a waveform around 8,192 × 50 µs long. If PS DDR is not feasible, but we could use PL DDR as the storage backing for the offload path, we could still reach around 1,024 × 50 µs.

In short, our main goal is to increase the number of samples we can store and replay, so we can generate a much longer continuous signal. If there is an alternative approach (for example, another architecture to stream data, a different buffering method, or a recommended HDL/software path), we are completely open to it.

Thank you very much for your support. If anything is unclear or if you need more details about our setup, I’d be happy to provide them.

Hi,

Why did you choose the operation Mode 10 for AD9172? I'm asking because one way to solve this would be to reduce the lane rate, therefore lowering the device_clk frequency from 368.64MHz to a value below 300MHz. You'd also have to reduce the DAC_DATA_WIDTH from 256 to 128 (in order to achieve a lower data rate on the DAC-FPGA side than the DMA-memory side).

Then, you increase the DMA-memory bandwidth by increasing the HP Port clock to 333 MHz @128b, the maximum value for zcu102. Here is a solution for this: https://github.com/analogdevicesinc/hdl/blob/42dc6a4feb9046115de19b85bde1f2fa849a0116/projects/daq3/zcu102/system_bd.tcl#L56

Finally, you set the data offload in bypass mode.

Please let me know if this scenario works in your case.

Regards,

Ionut