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AD9154-FMC-EBZ + ZCU102 => Ref RF signal input @ J1 doubt

Thread Summary

The user is integrating the AD9154-FMC-EBZ Eval board with the Xilinx ZCU102 and asks whether to feed a 2 GHz or 1.5 GHz RF sine signal at J1 for a DAC sampling rate of 1 GSa/s. The final answer suggests using a 2 GHz DACCLK and setting the interpolation factor to x2. The IIO Oscilloscope is not suitable for controlling the AD9154; an actual oscilloscope is needed to observe the analog output, and the sampling rate and signal frequency must be configured in the reference design code.
AI Generated Content
Category: Software
Product Number: AD9154

Hi,

I am working on integrating AD9154-FMC-EBZ Eval board with Xilinx ZCU102.

This user-guide recommends feeding 1.5GHz RF sine signal @ J1 => EVALUATING THE AD9154 DIGITAL-TO-ANALOG CONVERTER [Analog Devices Wiki]

However, I found out from the device tree that the Ref clock freq is 0x77359400 = 2 GHz:

dtc -I fs /sys/firmware/devicetree/base -O dts 2>/dev/null | grep -B 10 "phandle = <0x29>" | head -30

clocks {

clock@0 {
clock-output-names = "clkin";
#clock-cells = <0x00>;
clock-frequency = <0x77359400>;
compatible = "fixed-clock";
phandle = <0x29>;

Now, my question is whether I should feed 2GHz OR 1.5GHz at J1 of AD9154-FMC-EBZ Eval board

Note: I plan to use ADF4351 Signal Generator to feed this RF signal

I am aiming for DAC Sampling rate of 1GSa/s

==================================================================

/sys/bus/iio/devices/iio:device1/out_altvoltage1_frequency

  • OUT1: 2000 MHz (DACCLK to AD9154)
  • OUT6: 31 MHz (SYSREF1)
  • OUT7: 31 MHz (SYSREF2)
  • OUT9: 250 MHz (GBTCLK to FPGA)

Next question is: I plan to use IIO Oscilloscope later to ctrl AD9154-FMC-EBZ, can I adjust Sampling rate & Signal freq and other parameters using it?

OS Details:

root@analog:/home# cat /etc/os-release
PRETTY_NAME="Kuiper GNU/Linux 11.2 (bullseye)"
NAME="Kuiper GNU/Linux"
VERSION_ID="11.2"
VERSION="11.2 (bullseye)"
VERSION_CODENAME=bullseye
ID=raspbian
ID_LIKE=debian
HOME_URL="">github.com/.../adi-kuiper-gen"
SUPPORT_URL="">ez.analog.com/.../"
root@analog:/home# uname -a
Linux analog 6.12.0 #1 SMP Fri Sep 5 10:43:56 UTC 2025 aarch64 GNU/Linux

Thanks

Thread Notes

  • ADI North America will be on winter shutdown starting December 24, 2024; perhaps another community member can assist you until our return on January 2, 2025.
  • Hi  ,

    Thank you for your interest in AD9154. Someone from the FPGA Reference Designs group will respond to your query regarding the ADI Kuiper Linux reference code, but likely it will be after the holidays. Thank you very much for your patience. 

    Best regards~

  • Hi @FPGA Reference Designs group, can you please clarify my questions?

    Thanks 

  • Hi  ,

    Apologies for the delay. Based on your description, a 2GHz DACCLK might be more appropriate, then set the Interpolation factor to x2 to get a sampling rate of 1GSPS. Also check that the CLK you plan to inject to the EVB is the same as what's written in the reference design code. The UG you linked for AD9154 is just an example procedure.  

    For your other question, I believe IIO Oscilloscope is just like an oscilloscope instrument, but for plotting/visualizing output data for Linux systems. You can perform register read/writes using this tool and you can visualize the output of the IIO device (AD9154 EVB) in the time domain. However, I'm not sure you can control the sampling rate and signal frequency in ADI IIO Oscilloscope, rather you should use PyADI-IIO (a Python abstraction module for ADI hardware with IIO drivers) to modify parameters such as the sampling rate and output signal frequency in the reference design code. The IIO driver reference design codes are located here: AD914x GitHub Linux Driver Source Code.

    cc:  and team in case you have any other questions.

    Best regards,
    Marco

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