Reg usage of AD9467-FMC-250EBZ with VC707 FPGA

Hello rajkun ,

Here is the HDL design for the ad9467_fmc and its documentation. 

Note that in the main branch we no longer have support for vc707. For the HDL_2023_R3 release we use Vivado 2023.2. Take a look at the documentation on how to build the HDL design, along with the steps on how to port projects on other FPGA carrier. 

The common base design for the vc707 can be found here.

Did you encounter any specific issues while trying to build the design? If so, please provide more details so that we can help you further.

Kind regards,

Stanca

Actually, I am new to working with an FPGA. I needed some guidance regarding (considering I am able to port the setting for some other board to this) how to use either Xilinx ISE/ Vivado to generate bitstream for proper communication of the ADC Evaluation board with the FPGA and in turn with a computer for DAQ. Any and all help regarding this will be greatly appreciated.

Got it. You can start by reading the documentation. It should guide you on how to use our repository, build the desired project up to generating the bitstream in Vivado.

If you encounter any issues in the process, let us know.

Hello rajkun ,

Do you have any follow up questions, or can we close this thread?

Kind regards,

Stanca

Closing this thread due to inactivity.