Noisy Input from EVAL-ADAQ23878

Hello,

Based on your previous thread on this topic, could you let us know it the HDL design that you are now using is the custom version from the pdf attachment, where the axi_ltc2387 and axi_dmac instances have been added from the HDL_2023_R2 sources? Did you do any other modifications since then? 

Regarding the test results:

Did you use one lane mode or two lanes? 

Also, could you try feeding a 0.5MHz sinewave and attach the plot?

Kind regards,

Stanca

Hi Stanca,

Yes, it is the same HDL design I posted before. I didn't do other modifications. 

It is in two lanes mode, does it make any difference in the noise levels?

Ok, I will try the sine in a bit and get back to you.

Kind regards,

Vitor.

I collected data for 500Khz and 1MHz, 1024 samples. The sine wave is 5Vpp, generated by ADALM2000.
I have attached the data in the .zip file. Here is a screenshot for 500KHz:

adaq23878-tests.zip

I see. I am currently working on improving this design, I can't give you an accurate estimation on how long it's gonna take. Currently, this design should work at 15Msps on two lanes and at 7.5Msps for one lane. Regarding the CNV and CLK_GATE signals, in our reference design they are generated using the axi_pwm_gen IP, we don't use the onboard PLLs. 

In the meantime, you could try to take a look into our design and include the axi_pwm_gen in HDL in software.

Hi Stanca,

Do you have any recommendations for improving the noise?
I assume by onboard PLL you mean AD9513? Any reason for not using it? I could try to switch to generating CNV as well, I thought using the AD9513 output directly would give less jitter since the clock does not have to go through the FPGA fabric and the FMC connector.

I am planning on using the EVAL board for some experiments, including AM and FM-AFM, so will be implementing a PLL with it on the FPGA, max planned bandwidth is 1MHz.

The reason why we are not using the onboard clock chip is because it is not easily configurable. If you manage to configure it, that's great, but unfortunately we cannot guide you as we do not support this feature.

Another thing that I noticed in your custom design is that the clk_gate signal doesn't seem to be generated anywhere. The axi_ltc2387 IP expects to receive the clk_gate input. 

If you want to use AD9513 to generate the clock, it should generate the conversion signal (cnv), the clock gate signal (clk_gate) and the reference clock (ref_clk).

Also note that you will need to have a phase shift between the cnv and the clk_gate signals.

Due to this complexity, we preferred to use the axi_pwm_gen instead.

I couldn't get the TESTPAT reliably with the axi_pwm_gen IP before while using the CNV from AD9513, not even at 8.33MSps. Tried many different settings.

In my design from before the clk_gate is generated by my own pulse_gen_adc IP, it's a small block that receives the ref_clk (120MHz) and adds the phase shift from CNV. The output is fed to a Xilinx BUFGCE which gates the lvds clock (60MHz in TWOLANES mode, generated from ref_clk). It all works well with AD9513 configured for 8.33MSps, TESTPAT always comes up if enabled but again the problem is that I am getting quite a bit of noise.

So if I drop the AD9513 and generate CNV in the FPGA should I be able to match the ADAQ23878 specs on the datasheet at 15MSps, using the design you propose?
 

We tested this setup on two lanes at 15Msps, with our configuration. But take a look at the entire design, including the timing constraints.

Hi Stanca,

Tried sticking to the original design as much as possible, but that only gave me the test pattern intermittently at 15Msps. Also tried a lower sampling rate of 8.57Msps, but got the same result.
I have a few questions about the reference project:

• The ref_clk on cn0577 is 120MHz but in the EVAL board it is 100MHz, did you test with that 100MHz clock?
• The reference project also outputs cnv_en which is the cnv signal to be cleaned by the flip-flop on the adc board, but that is disabled on eval-adaq23878. In cn0577 do you use that or the generated lvds cnv?

Also tried both keeping the ref_clk at 100 and adding a pll block to get 120.

vivado project

block diagram pdf

For the adaq2387x boards, the ref_clk is indeed 100MHz. To meet the timing specifications, we also increased the frequency to 120MHz. The HDL project is still under development, as we noticed that the design created initially for cn0577 isn't straight forward to be used with the adaq2387x boards.

Regarding cnv_en, for the cn0577 project, it is tied to the cnv signal hdl/projects/cn0577/zed/system_top.v at main · analogdevicesinc/hdl, but for the conversion signal generation we use the axi_pwm_gen: hdl/projects/cn0577/common/cn0577_bd.tcl at main · analogdevicesinc/hdl, so we control it from there.