Adapting AD4134-FMC HDL Project from Zedboard to UltraZed-EG

Hi gorogh ,

Can you please let us know what is the no-OS project you are starting from?

You could use the cn0561 project: https://github.com/analogdevicesinc/no-OS/tree/main/projects/cn0561

For running the project on a ZedBoard you will have to omit the cs_sync_pin by ommenting the following lines in the ad713x driver: https://github.com/analogdevicesinc/no-OS/blob/3abe99ba579ccbd164c6a5a702f454648607c863/drivers/adc/ad713x/ad713x.c#L416-L418

You will then have to update the contents of the parameters.h file with the definitions in your HDL.

Regards,

G

Hello G,

Thank you for getting back to me and for providing the troubleshooting steps.

I’m currently using a modified version of the ad7134_fmc HDL project and starting from the ad7134_fmcz no-OS project. I’ve updated the parameters.h file with what I believe are the correct values. Attached is a ZIP file containing both the parameters.h and xparameters.h files.

During further testing, I found that reducing the number of samples per channel from 1024 to 256 (via the AD7134_FMC_SAMPLE_NO definition in parameters.h) prevents garbage output in the PuTTY console. However, attempting to read more than 256 samples consistently results in the following error:
"Error transferring data using DMA."

I haven’t yet tried using the cn0561 no-OS project to gather data from the board, but I was previously able to adapt the ad7134_fmcz no-OS project to work with the AD4134 and Zedboard, so I suspect the issue may lie in the modified HDL project or possibly incorrect parameter settings.

I also tried your suggestion of omitting the cs_sync_pin by commenting out the relevant lines in the code (based on the ad7134_fmcz project), but the same DMA read error persists. Next, I plan to try adapting the cn0561 no-OS project to work with my current HDL design. If that doesn't succeed, I’ll attempt to modify the cn0561 HDL project itself. To clarify—is the cn0561 no-OS project compatible with the ad7134_fmc HDL project?

Best regards,
Paul

1323.parameters.zip

Hi gorogh ,

You can find out more about project compatibility here:  Adapting AD4134-FMC HDL Project from Zedboard to KCU105

Regards,

G

Hi danmois ,

I'm working with Paul on the project. We started with the example HDL and no-OS using the Zedboard and had Eval-AD4134 work properly. Then, we began to try KCU105 or Ultrazed-EG for our complete design with multiple AD4134 chips.

Since you mentioned in the above post that it may be difficult to adapt to KCU105, we decided to try Ultrazed-EG, which is an MPSoC series similar to the Zynq 7000 series on the Zedboard. Paul adapted the HDL and the no-OS that work for the Zedboard to Ultrazed-EG, but ran into the errors described in his post. We would appreciate your advice on the debugging of the adaptation to MPSoC.

Is there any example of using ZCU102 with AD4134?

Thanks,

Zepeng

Hi,

So far we only have AD4134 HDL support for the Zedboard and Cora-z7s, both are zynq 7 series FPGAs, not MPSOCs. We do not have ZCU102 support for AD4134.

~Sergiu

Hi sarpadi ,

Is there a difference in how PS8 handles SPI vs the PS7? zepengli and I had attempted to use the UltraZed-EG because it does not use Microblaze and has a PS block. If I wanted to adapt the HDL to work with the UltraZed-EG, would I have to replace the PS8 SPI with a Xilinx QSPI controller in standard mode? Or is there a difference in memory that we have not considered when trying to port the HDL design from the zedboard to the UltraZed-EG?

Thanks,

Paul

Hi sarpadi danmois ,

We were able to modify the HDL for the Zedboard to Ultrazed-eg and compile it in Vivado, then compile no-OS with the exported hardware. The output from no-OS on the Zedboard is correct, but all the ADC values are zero with the ultrazed-eg board. I measured DCLK, ODR, DOUT0, and DOUT1 with a scope. The measurement seems ok and is consistent with the Zedboard. The data stream was not written to memory with axi_dma?

Thanks,

Zepeng

Hi zepengli ,

I can talk mostly regarding the software part. One thing that you could first try is to enable debug messages over UART, so you will get a better idea about what is going on. For this, specify DEBUG level here: https://github.com/analogdevicesinc/no-OS/blob/c7abf1b39890b50a0d1445fcffe22af6a1240c16/include/no_os_print_log.h#L49

Then, for a better view of the program flow, you should debug your code with the available Vitis debugger.

Regards,

G

Hi

Can you access the part's register map? Are you reading values that make sense when compared to the regmap in the datasheet? Can you access the scratch pad (0xA)? This is what I would look for first if you have doubts about the SPI interface.

Have you checked if the timing specifications are met?
https://www.analog.com/media/en/technical-documentation/data-sheets/ad4134.pdf pg.11 fix.2 shows the timing diagram

The relation between ODR and DCLK is very important. Also check the ODR high time and frequency to make sure it matches what you expect to achieve.

Do you have any experience with ILA? It is a very useful tool for debugging projects like this. It may answer most of your questions especially on the HDL side (you can even check timing with it)

~Sergiu

Hi zepengli , gorogh! Do you have any updates? Did you manage to solve your issues?