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AD9083 Recommended for New Designs
The AD9083 is a 16-channel, 125 MHz bandwidth, continuous time Σ-Δ (CTSD) ADC. The device features an on-chip, programmable, single-pole antialiasing...
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ZCU102 to ZCU111 migration 9083evb project GTYE4 timing error

		
	
				

			

									
					    omer
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jul 15, 2025 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user encountered timing errors when migrating an AD9083EVB project from ZCU102 to ZCU111. The final answer suggests using the Transceiver Wizard to check the util_adxcvr configuration and trying different placement and timing optimization strategies, such as Performance_RefinePlacement or Performance_ExtraTimingOpt. The user's constraints for the refclk clock and other pins are provided, and the engineer recommends verifying these constraints.
                        	    

                
                     AI Generated Content
                
    	    

             
				
        		

		    
		    		    

		      		            		        
Category: Hardware

    		        		            		    
Product Number:  AD9083  

    		        		    		    

		    		    
		    			

			    
Hello Everyone, 


I have created the AD9083EVB project using the usual tcl flow successfully for ZCU102 board and then made a copy of it to migrate via GUI to another board we already have and I have done the following:


--In the system settings Change the Board to ZCU111


--Change the constraint files pin locations to match the FMC connector on the ZCU111 board instead of the ZCU102 board


--Recreate the system_bd for the new device


--change the axi_ad9083rx_xcvr and util_ad9083_xcvr Xcvr Type setting to GTYE4 (from GTHE4)


Project built, bitstream created but had the attached timing errors on GTYE4 related part.


It seemed to me that the timing errors more due to net delays and seemed a bit strange since the placement of FFs looked close to the GTYE4 site.


I thought may be I missed to make some more relevant changes on the receiver IP settings. Or may be am I missing to edit any other constraints?


Any ideas here that would help? 




Kind Regards,


Ömer.


  

			

			
									
		                             
                        

    

                                            
                 GTYE4
                
                                                    
                 hardware
                
                                                    
                 migration
                
                                                    
                 High Speed A/D Converters >10 MSPS
                
                                                    
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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Jul 16, 2025 3:34 AM
            
            
						
			            		
    
		
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    Hi Ömer,
    

    It is a bit odd that it is failing like this...
    

    A couple of ideas:
    

      

    • Have you used the Transceiver Wizard? Could you try using it, and see if you initially missed some values in the configuration of util_adxcvr?
      • 

    • Could you try using a different strategy, maybe Performance_RefinePlacement or Performance_ExtraTimingOpt? You have the documentation for these in Xilinx UG904. And here you have an example of how we set the strategy.
      • 

    • How did you constrain the refclk clock?
      • 

    

    Best regards,
    Iulia
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jul 16, 2025 4:03 AM
            
            
												
						in reply to iulia
					
										
			            		
    
		
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    Hello iulia, thank you for your reply. 
    

    - I will try using the Transciever Wizard, is there a guideline to generate something and compare it to the util_adxcvr configuration?
    

    - I will also try the different strategies. 
    

     -- Update: Performance_ExtraTimingOpt did not change anything. 
    

    - My modified system_constr.xdc is like this:
    

    - 
    ###############################################################################
## Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################

# ad9083

#input
set_property  -dict {PACKAGE_PIN  AP9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE}       [get_ports glblclk_p]       ; ## FMC_HPC0_LA00_CC_P
set_property  -dict {PACKAGE_PIN  AR9  IOSTANDARD LVDS DIFF_TERM_ADV TERM_100 DQS_BIAS TRUE}       [get_ports glblclk_n]       ; ## FMC_HPC0_LA00_CC_N

#set_property PACKAGE_PIN AP9      [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank  65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65
#set_property IOSTANDARD  LVDS     [get_ports "FMCP_HSPC_LA00_CC_P"] ;# Bank  65 VCCO - VADJ_FMC - IO_L14P_T2L_N2_GC_65
#set_property PACKAGE_PIN AR8      [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank  65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65
#set_property IOSTANDARD  LVDS     [get_ports "FMCP_HSPC_LA01_CC_N"] ;# Bank  65 VCCO - VADJ_FMC - IO_L13N_T2L_N1_GC_QBC_65

set_property  -dict {PACKAGE_PIN  W33}                        [get_ports ref_clk0_p]      ; ## FMC_HPC0_GBTCLK0_M2C_C_P
set_property  -dict {PACKAGE_PIN  W34}                        [get_ports ref_clk0_n]      ; ## FMC_HPC0_GBTCLK0_M2C_C_N

set_property  -dict {PACKAGE_PIN  N38}                        [get_ports rx_data_p[0]]    ; ## FMC_HPC0_DP0_M2C_P
set_property  -dict {PACKAGE_PIN  N39}                        [get_ports rx_data_n[0]]    ; ## FMC_HPC0_DP0_M2C_N
set_property  -dict {PACKAGE_PIN  M36}                        [get_ports rx_data_p[1]]    ; ## FMC_HPC0_DP1_M2C_P
set_property  -dict {PACKAGE_PIN  M37}                        [get_ports rx_data_n[1]]    ; ## FMC_HPC0_DP1_M2C_N
set_property  -dict {PACKAGE_PIN  L38}                        [get_ports rx_data_p[2]]    ; ## FMC_HPC0_DP2_M2C_P
set_property  -dict {PACKAGE_PIN  L39}                        [get_ports rx_data_n[2]]    ; ## FMC_HPC0_DP2_M2C_N
set_property  -dict {PACKAGE_PIN  K36}                        [get_ports rx_data_p[3]]    ; ## FMC_HPC0_DP3_M2C_P
set_property  -dict {PACKAGE_PIN  K37}                        [get_ports rx_data_n[3]]    ; ## FMC_HPC0_DP3_M2C_N

set_property  -dict {PACKAGE_PIN  AL12  IOSTANDARD LVCMOS18}   [get_ports spi_csn_clk]     ; ## FMC_HPC0_LA07_N
set_property  -dict {PACKAGE_PIN  AH13  IOSTANDARD LVCMOS18}   [get_ports spi_csn_adc]     ; ## FMC_HPC0_LA02_P
set_property  -dict {PACKAGE_PIN  AP8 IOSTANDARD LVCMOS18}   [get_ports spi_clk]         ; ## FMC_HPC0_LA01_CC_P
set_property  -dict {PACKAGE_PIN  AR8 IOSTANDARD LVCMOS18}   [get_ports spi_sdio]        ; ## FMC_HPC0_LA01_CC_N

set_property  -dict {PACKAGE_PIN  AJ13  IOSTANDARD LVCMOS18}   [get_ports pwdn]            ; ## FMC_HPC0_LA02_N
set_property  -dict {PACKAGE_PIN  AK13  IOSTANDARD LVCMOS18}   [get_ports rstb]            ; ## FMC_HPC0_LA07_P
set_property  -dict {PACKAGE_PIN  AJ12  IOSTANDARD LVCMOS18}   [get_ports refsel]          ; ## FMC_HPC0_LA03_P

set_property  -dict {PACKAGE_PIN  AG12 IOSTANDARD LVDS}       [get_ports rx_sync_p]       ; ## FMC_HPC0_LA04_P
set_property  -dict {PACKAGE_PIN  AH12 IOSTANDARD LVDS}       [get_ports rx_sync_n]       ; ## FMC_HPC0_LA04_N

set_property  -dict {PACKAGE_PIN  AL9  IOSTANDARD LVDS}       [get_ports sysref_p]        ; ## FMC_HPC0_LA08_P
set_property  -dict {PACKAGE_PIN  AM9  IOSTANDARD LVDS}       [get_ports sysref_n]        ; ## FMC_HPC0_LA08_N

# clocks
create_clock -period 2 -name rx_ref_clk [get_ports ref_clk0_p]
create_clock -period 8 -name rx_ref_clk2 [get_ports glblclk_p]

set_input_delay -clock [get_clocks rx_ref_clk2] [get_property PERIOD [get_clocks rx_ref_clk2]] \
                [get_ports -regexp -filter { NAME =~  ".*sysref.*" && DIRECTION == "IN" }]

    

    

    There are 3 critical timing warnings due to the following constraints:
    

     
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jul 16, 2025 5:26 AM
            
            
												
						in reply to omer
					
										
			            		
    
		
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    Update : 
    

    Performance_ExtraTimingOpt did not change anything.
    

    Performance_RefinePlacement did not change the situation as well.
    

    There are 3 critical timing warnings due to the 3 constraints below:
    

     
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Jul 16, 2025 6:28 AM
            
            
												
						in reply to omer
					
										
			            		
    
		
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    Update. I have tried to create Transciever files using the GUI settings as below:
    

     
    

    

     I compared the attributes, (there are much less in the util_adxcvr set from the upper module and skipped the ones that does not set by the util_adxcvr_xcm. v file, I assume the defaults and same but have no clue.) The comparison shows some differences but I am not sure if my GUI settings are correct at first place.
    

    Just putting here the 2 files as well. 
    

    



    
    
    
        Fullscreen
        ad_util_adxcvr_xcm_attrbitues.txt
        Download
    
    
    
    GTYE4_COMMON #(
      .AEN_QPLL0_FBDIV (1'b1),
      .AEN_QPLL1_FBDIV (1'b1),
      .AEN_SDM0TOGGLE (1'b0),
      .AEN_SDM1TOGGLE (1'b0),
      .A_SDM0TOGGLE (1'b0),
      .A_SDM1DATA_HIGH (9'b000000000),
      .A_SDM1DATA_LOW (16'b0000000000000000),
      .A_SDM1TOGGLE (1'b0),
      .BIAS_CFG0 (16'b0000000000000000),
      .BIAS_CFG1 (16'b0000000000000000),
      .BIAS_CFG2 (16'b0000000100100100),
      .BIAS_CFG3 (16'b0000000001000001),
      .BIAS_CFG4 (16'b0000000000010000),
      .BIAS_CFG_RSVD (16'b0000000000000000),
      .COMMON_CFG0 (16'b0000000000000000),
      .COMMON_CFG1 (16'b0000000000000000),
      .POR_CFG (16'b0000000000000000),
      .PPF0_CFG (16'b0000011000000000),
      .PPF1_CFG (16'b0000011000000000),
      .QPLL0CLKOUT_RATE ("HALF"),
      .QPLL0_CFG0 (16'b0011001100011100),
      .QPLL0_CFG1 (16'b1101000000111000),
      .QPLL0_CFG1_G3 (16'b1101000000111000),
      .QPLL0_CFG2 (16'b0000111111000000),
      .QPLL0_CFG2_G3 (16'b0000111111000000),
      .QPLL0_CFG3 (16'b0000000100100000),
      .QPLL0_CFG4 (16'b0000000000000011),
      .QPLL0_CP (10'b0011111111),
      .QPLL0_CP_G3 (10'b0000001111),
      .QPLL0_FBDIV (10'b0000110000),
      .QPLL0_FBDIV_G3 (160),
      .QPLL0_INIT_CFG0 (16'b0000001010110010),
      .QPLL0_INIT_CFG1 (8'b00000000),
      .QPLL0_LOCK_CFG (16'b0010010111101000),
      .QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
      .QPLL0_LPF (10'b0100110111),
      .QPLL0_LPF_G3 (10'b0111010101),
      .QPLL0_PCI_EN (1'b0),
      .QPLL0_RATE_SW_USE_DRP (1'b1),
      .QPLL0_REFCLK_DIV (1),
      .QPLL0_SDM_CFG0 (16'b0000000010000000),
      .QPLL0_SDM_CFG1 (16'b0000000000000000),
      .QPLL0_SDM_CFG2 (16'b0000000000000000),
      .QPLL1CLKOUT_RATE ("HALF"),
      .QPLL1_CFG0 (16'b0011001100011100),
      .QPLL1_CFG1 (16'b1101000000111000),
      .QPLL1_CFG1_G3 (16'b1101000000111000),
      .QPLL1_CFG2 (16'b0000111111000000),
      .QPLL1_CFG2_G3 (16'b0000111111000000),
      .QPLL1_CFG3 (16'b0000000100100000),
      .QPLL1_CFG4 (16'b0000000000000011),
      .QPLL1_CP (10'b0011111111),
      .QPLL1_CP_G3 (10'b0001111111),
      .QPLL1_FBDIV (10'b0000110000),
      .QPLL1_FBDIV_G3 (80),
      .QPLL1_INIT_CFG0 (16'b0000001010110010),
      .QPLL1_INIT_CFG1 (8'b00000000),
      .QPLL1_LOCK_CFG (16'b0010010111101000),
      .QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
      .QPLL1_LPF (10'b1000011111),
      .QPLL1_LPF_G3 (10'b0111010100),
      .QPLL1_PCI_EN (1'b0),
      .QPLL1_RATE_SW_USE_DRP (1'b1),
      .QPLL1_REFCLK_DIV (1),
      .QPLL1_SDM_CFG0 (16'b0000000010000000),
      .QPLL1_SDM_CFG1 (16'b0000000000000000),
      .QPLL1_SDM_CFG2 (16'b0000000000000000),
      .RSVD_ATTR0 (16'b0000000000000000),
      .RSVD_ATTR1 (16'b0000000000000000),
      .RSVD_ATTR2 (16'b0000000000000000),
      .RSVD_ATTR3 (16'b0000000000000000),
      .RXRECCLKOUT0_SEL (2'b00),
      .RXRECCLKOUT1_SEL (2'b00),
      .SARC_ENB (1'b0),
      .SARC_SEL (1'b0),
      .SDM0INITSEED0_0 (16'b0000000100010001),
      .SDM0INITSEED0_1 (9'b000010001),
      .SDM1INITSEED0_0 (16'b0000000100010001),
      .SDM1INITSEED0_1 (9'b000010001),
      .SIM_MODE ("FAST"),
      .SIM_RESET_SPEEDUP ("TRUE"),
      .SIM_DEVICE ("ULTRASCALE_PLUS"),
      .UB_CFG0 (16'b0000000000000000),
      .UB_CFG1 (16'b0000000000000000),
      .UB_CFG2 (16'b0000000000000000),
      .UB_CFG3 (16'b0000000000000000),
      .UB_CFG4 (16'b0000000000000000),
      .UB_CFG5 (16'b0000010000000000),
      .UB_CFG6 (16'b0000000000000000))
    

    





    
    
    
        Fullscreen
        wizard_created_attributes.txt
        Download
    
    
    
     #(
  .AEN_QPLL0_FBDIV                 (1'b1),
  .AEN_QPLL1_FBDIV                 (1'b1),
  .AEN_SDM0TOGGLE                  (1'b0),
  .AEN_SDM1TOGGLE                  (1'b0),
  .A_SDM0TOGGLE                    (1'b0),
  .A_SDM1DATA_HIGH                 (9'b000000000),
  .A_SDM1DATA_LOW                  (16'b0000000000000000),
  .A_SDM1TOGGLE                    (1'b0),
  .BIAS_CFG0                       (16'b0000000000000000),
  .BIAS_CFG1                       (16'b0000000000000000),
  .BIAS_CFG2                       (16'b0000000100100100),
  .BIAS_CFG3                       (16'b0000000001000001),
  .BIAS_CFG4                       (16'b0000000000010000),
  .BIAS_CFG_RSVD                   (16'b0000000000000000),
  .COMMON_CFG0                     (16'b0000000000000000),
  .COMMON_CFG1                     (16'b0000000000000000),
  .POR_CFG                         (16'b0000000000000000),
  .PPF0_CFG                        (16'b0000100000000000),
  .PPF1_CFG                        (16'b0000011000000000),
  .QPLL0CLKOUT_RATE                ("HALF"),
  .QPLL0_CFG0                      (16'b0011001100011100),
  .QPLL0_CFG1                      (16'b1101000000111000),
  .QPLL0_CFG1_G3                   (16'b1101000000111000),
  .QPLL0_CFG2                      (16'b0000111111000001),
  .QPLL0_CFG2_G3                   (16'b0000111111000001),
  .QPLL0_CFG3                      (16'b0000000100100000),
  .QPLL0_CFG4                      (16'b0000000000000010),
  .QPLL0_CP                        (10'b0011111111),
  .QPLL0_CP_G3                     (10'b0000001111),
  .QPLL0_FBDIV                     (25),
  .QPLL0_FBDIV_G3                  (160),
  .QPLL0_INIT_CFG0                 (16'b0000001010110010),
  .QPLL0_INIT_CFG1                 (8'b00000000),
  .QPLL0_LOCK_CFG                  (16'b0010010111101000),
  .QPLL0_LOCK_CFG_G3               (16'b0010010111101000),
  .QPLL0_LPF                       (10'b1101111111),
  .QPLL0_LPF_G3                    (10'b0111010101),
  .QPLL0_PCI_EN                    (1'b0),
  .QPLL0_RATE_SW_USE_DRP           (1'b1),
  .QPLL0_REFCLK_DIV                (1),
  .QPLL0_SDM_CFG0                  (16'b0000000010000000),
  .QPLL0_SDM_CFG1                  (16'b0000000000000000),
  .QPLL0_SDM_CFG2                  (16'b0000000000000000),
  .QPLL1CLKOUT_RATE                ("HALF"),
  .QPLL1_CFG0                      (16'b0011001100011100),
  .QPLL1_CFG1                      (16'b1101000000111000),
  .QPLL1_CFG1_G3                   (16'b1101000000111000),
  .QPLL1_CFG2                      (16'b0000111111000011),
  .QPLL1_CFG2_G3                   (16'b0000111111000011),
  .QPLL1_CFG3                      (16'b0000000100100000),
  .QPLL1_CFG4                      (16'b0000000000000010),
  .QPLL1_CP                        (10'b0011111111),
  .QPLL1_CP_G3                     (10'b0001111111),
  .QPLL1_FBDIV                     (66),
  .QPLL1_FBDIV_G3                  (80),
  .QPLL1_INIT_CFG0                 (16'b0000001010110010),
  .QPLL1_INIT_CFG1                 (8'b00000000),
  .QPLL1_LOCK_CFG                  (16'b0010010111101000),
  .QPLL1_LOCK_CFG_G3               (16'b0010010111101000),
  .QPLL1_LPF                       (10'b1000011111),
  .QPLL1_LPF_G3                    (10'b0111010100),
  .QPLL1_PCI_EN                    (1'b0),
  .QPLL1_RATE_SW_USE_DRP           (1'b1),
  .QPLL1_REFCLK_DIV                (1),
  .QPLL1_SDM_CFG0                  (16'b0000000010000000),
  .QPLL1_SDM_CFG1                  (16'b0000000000000000),
  .QPLL1_SDM_CFG2                  (16'b0000000000000000),
  .RSVD_ATTR0                      (16'b0000000000000000),
  .RSVD_ATTR1                      (16'b0000000000000000),
  .RSVD_ATTR2                      (16'b0000000000000000),
  .RSVD_ATTR3                      (16'b0000000000000000),
  .RXRECCLKOUT0_SEL                (2'b00),
  .RXRECCLKOUT1_SEL                (2'b00),
  .SARC_ENB                        (1'b0),
  .SARC_SEL                        (1'b0),
  .SDM0INITSEED0_0                 (16'b0000000100010001),
  .SDM0INITSEED0_1                 (9'b000010001),
  .SDM1INITSEED0_0                 (16'b0000000100010001),
  .SDM1INITSEED0_1                 (9'b000010001),
  .SIM_DEVICE                      ("ULTRASCALE_PLUS"),
  .SIM_MODE                        ("FAST"),
  .SIM_RESET_SPEEDUP               ("TRUE"),
  .UB_CFG0                         (16'b0000000000000000),
  .UB_CFG1                         (16'b0000000000000000),
  .UB_CFG2                         (16'b0000000000000000),
  .UB_CFG3                         (16'b0000000000000000),
  .UB_CFG4                         (16'b0000000000000000),
  .UB_CFG5                         (16'b0000010000000000),
  .UB_CFG6                         (16'b0000000000000000)
)
    

    


    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    •  Super User  
    
            
						
                            
            
            				
            
                on Jul 16, 2025 6:52 AM
            
            
						
			            		
    
		
										0
					
	
    

		
		
    
		
    
                                
                                                            
    
					
    omer said:
    I will try using the Transciever Wizard, is there a guideline to generate something and compare it to the util_adxcvr configuration?
    

    Sorry, I forgot to link it: https://analogdevicesinc.github.io/hdl/library/jesd204/xgt_wizard/index.html 
    

    I will try to take a look at this in more detail these days. Thanks for the information.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 5, 2025 3:39 AM
            
            
												
						in reply to iulia
					
										
			            		
    
		
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    Hello  , any comments or ideas about the attributes of the GTYE4 component created by the wizard and the AD flow? 
    

    I still have the issue.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 6, 2025 4:09 AM
            
            
												
						in reply to omer
					
										
			            		
    
		
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    Hi Ömer,
    

    The attributes in util_adxcvr should reflect the attributes you generated using the Transceiver Wizard. I suggest you look at the util_adxcvr IP in the block design and check the parameters one by one. Try to find the corresponding wizard generated attribute for each one. Any value that doesn't match, you edit it in the util_adxcvr.
    

    Best regards,
    Andrei
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 14, 2025 8:18 AM
            
            
						
			            		
    
		
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    Hi  ,
    

    Have you made any progress on this?
    

    Regards, Elena
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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                on Aug 15, 2025 9:35 AM
            
            
												
						in reply to elenahadarau
					
										
			            		
    
		
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    Hello  ,
    

    No unfortunately. I have seen some differences on the attributes ( previously sent 2 txt files to show the differences) but first I am not sure what I am creating from the GUI would match with what AD JESD204 interface requires from the Transceiver (I have sent also the GUI settings from the moment I was creating the xcvr from wizard).
    

    Second, I am not sure where to edit these customization of the attributes (source at rtl generation or  on a script? )
    

    If you could help on this, I would appreciate. I will need to do this also for some other FPGAs as well very soon.
    

    

    Best Regards,
    

    Ömer.
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
						
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 26, 2025 8:54 AM
            
            
												
						in reply to omer
					
										
			            		
    
		
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    Hi Ömer,
    

    The way you generated the attributes looks good. Next step is to add those to the util_adxcvr IP. There are two ways to do this. 
    

     - The first way is to open the block diagram in Vivado, find the util_adxcvr IP and add them manually. Here you can find some more information about these parameters: UTIL_ADXCVR - Configuration Parameters 
    

     - The other way is to write them directly in the tcl files. Here's an example on how to do this: ad9213_evb/vcu118/system_bd.tcl
    

    Best regards,
    Andrei
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
				
						
						
				
				
		
		
    
			
		
    
	
    

    

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