adrv9026 +ZCU102 HDL no-OS reference design (Vivado)

The issue here is that you are using the ignore version check as a build parameter, but it is an environment variable that needs to be exported separately. Please follow these instructions in your terminal:

export ADI_IGNORE_VERSION_CHECK=1

make

still failed. See my screenshot

Could you also add the Error message? 

From log file

### ad_connect gpio_i sys_ps8/emio_gpio_i
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_i> is being overridden by the user with net <gpio_i_1>. This pin will not be connected as a part of interface connection <GPIO_0>.
connect_bd_net /gpio_i /sys_ps8/emio_gpio_i
### ad_connect gpio_o sys_ps8/emio_gpio_o
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_o> is being overridden by the user with net <sys_ps8_emio_gpio_o>. This pin will not be connected as a part of interface connection <GPIO_0>.
connect_bd_net /gpio_o /sys_ps8/emio_gpio_o
### ad_connect gpio_t sys_ps8/emio_gpio_t
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_t> is being overridden by the user with net <sys_ps8_emio_gpio_t>. This pin will not be connected as a part of interface connection <GPIO_0>.
connect_bd_net /gpio_t /sys_ps8/emio_gpio_t
### ad_ip_instance ilconcat spi0_csn_concat
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell spi0_csn_concat
ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name spi0_csn_concat .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}"
(procedure "ad_ip_instance" line 7)
invoked from within
"ad_ip_instance ilconcat spi0_csn_concat"
(file "C:/hdl/projects/common/zcu102/zcu102_system_bd.tcl" line 112)

while executing
"source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl"
(file "system_bd.tcl" line 10)

while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 136)
invoked from within
"adi_project_create $project_name $mode $parameter_list $device $board"
(procedure "adi_project" line 80)
invoked from within
"adi_project adrv9026_zcu102 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
ORX_ENABLE [get_env_param ORX_ENABLE ..."
(file "system_project.tcl" line 37)
INFO: [Common 17-206] Exiting Vivado at Fri Oct 31 11:16:02 2025...

Thank you. We'll reproduce this build and get back to you soon.

Hello Socchiplet ,

We reproduced this issue and it looks like we have a problem using the HDL main with the 2023.2 Vivado Version because of this change: Update utility cores to inline hdl variants · analogdevicesinc/hdl@eadd7d6.

If you replace manually the ilconcat instances to xlconcat, everywhere in zcu102_system_bd.tcl, it should go past that error. 

I changed il to xl as you stated in the tcl file. Still fails. Here are some screen shots

user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
$ which vitis
/cygdrive/c/Xilinx/Vitis/2023.2/bin/vitis

user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
$ which vivado
/cygdrive/c/Xilinx/Vivado/2023.2/bin/vivado

user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
$ export ADI_IGNORE_VERSION_CHECK=1

user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
$ make
Building axi_clkgen library [/cygdrive/c/hdl/library/axi_clkgen/axi_clkgen_ip.lo OK
Building util_cdc library [/cygdrive/c/hdl/library/util_cdc/util_cdc_ip.log] ... OK
Building util_axis_fifo library [/cygdrive/c/hdl/library/util_axis_fifo/util_axis_fifo_ip.log] ... OK
Building axi_dmac library [/cygdrive/c/hdl/library/axi_dmac/axi_dmac_ip.log] ... OK
Building axi_sysid library [/cygdrive/c/hdl/library/axi_sysid/axi_sysid_ip.log] ... OK
Building interface definitions [/cygdrive/c/hdl/library/interfaces/interfaces_ip.log] ... OK
Building util_axis_fifo_asym library [/cygdrive/c/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.log] ... OK
Building data_offload library [/cygdrive/c/hdl/library/data_offload/data_offload_ip.log] ... OK
Building ad_ip_jesd204_tpl_adc library [/cygdrive/c/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log] ... OK
Building ad_ip_jesd204_tpl_dac library [/cygdrive/c/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log] ... OK
Building axi_jesd204_common library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log] ... OK
Building axi_jesd204_rx library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log] ... OK
Building axi_jesd204_tx library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log] ... OK
Building jesd204_common library [/cygdrive/c/hdl/library/jesd204/jesd204_common/jesd204_common_ip.log] ... OK
Building jesd204_rx library [/cygdrive/c/hdl/library/jesd204/jesd204_rx/jesd204_rx_ip.log] ... OK
Building jesd204_tx library [/cygdrive/c/hdl/library/jesd204/jesd204_tx/jesd204_tx_ip.log] ... OK
Building sysid_rom library [/cygdrive/c/hdl/library/sysid_rom/sysid_rom_ip.log] ... OK
Building util_do_ram library [/cygdrive/c/hdl/library/util_do_ram/util_do_ram_ip.log] ... OK
Building util_hbm library [/cygdrive/c/hdl/library/util_hbm/util_hbm_ip.log] ... OK
Building util_cpack2 library [/cygdrive/c/hdl/library/util_pack/util_cpack2/util_cpack2_ip.log] ... OK
Building util_upack2 library [/cygdrive/c/hdl/library/util_pack/util_upack2/util_upack2_ip.log] ... OK
Building axi_adxcvr library [/cygdrive/c/hdl/library/xilinx/axi_adxcvr/axi_adxcvr_ip.log] ... OK
Building util_adxcvr library [/cygdrive/c/hdl/library/xilinx/util_adxcvr/util_adxcvr_ip.log] ... OK
Building adrv9026_zcu102 project [/cygdrive/c/hdl/projects/adrv9026/zcu102/adrv9026_zcu102_vivado.log] ... FAILED
For details see /cygdrive/c/hdl/projects/adrv9026/zcu102/adrv9026_zcu102_vivado.log

make: *** [../../scripts/project-xilinx.mk:113: adrv9026_zcu102.sdk/system_top.xsa] Error 1

user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
$

detailed failure log

### ad_connect spi0_csn_concat/dout spi0_csn
connect_bd_net /spi0_csn_concat/dout /spi0_csn
### ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_sclk_o> is being overridden by the user with net <sys_ps8_emio_spi0_sclk_o>. This pin will not be connected as a part of interface connection <SPI_0>.
connect_bd_net /sys_ps8/emio_spi0_sclk_o /spi0_sclk
### ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_m_o> is being overridden by the user with net <sys_ps8_emio_spi0_m_o>. This pin will not be connected as a part of interface connection <SPI_0>.
connect_bd_net /sys_ps8/emio_spi0_m_o /spi0_mosi
### ad_connect sys_ps8/emio_spi0_m_i spi0_miso
WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_m_i> is being overridden by the user with net <spi0_miso_1>. This pin will not be connected as a part of interface connection <SPI_0>.
connect_bd_net /sys_ps8/emio_spi0_m_i /spi0_miso
### ad_connect sys_ps8/emio_spi0_ss_i_n VCC
WARNING: [Coretcl 2-175] No Catalog IPs found
ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell VCC_1
ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name VCC_1 .
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

while executing
"create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}"
(procedure "ad_ip_instance" line 7)
invoked from within
"ad_ip_instance ilconstant $cell_name"
invoked from within
"if {$cell eq ""} {
# Create new constant source
ad_ip_instance ilconstant $cell_name
set cell [get_bd_cells -quiet $cell_name]
set_pro..."
(procedure "ad_connect_int_get_const" line 17)
invoked from within
"ad_connect_int_get_const $name_a $width"
(procedure "ad_connect" line 84)
invoked from within
"ad_connect sys_ps8/emio_spi0_ss_i_n VCC"
(file "C:/hdl/projects/common/zcu102/zcu102_system_bd.tcl" line 121)

while executing
"source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl"
(file "system_bd.tcl" line 10)

while executing
"source system_bd.tcl"
(procedure "adi_project_create" line 136)
invoked from within
"adi_project_create $project_name $mode $parameter_list $device $board"
(procedure "adi_project" line 80)
invoked from within
"adi_project adrv9026_zcu102 0 [list \
JESD_MODE [get_env_param JESD_MODE 8B10B ] \
ORX_ENABLE [get_env_param ORX_ENABLE ..."
(file "system_project.tcl" line 37)
INFO: [Common 17-206] Exiting Vivado at Tue Nov 4 07:10:05 2025...

It would be great if you can provide input on this as still build fails. We are stuck at build stage. Thanks

It would be great if you can provide input on this as still build fails. We are stuck at build stage. Thanks

Hello, we are sorry for the long wait. We discussed this situation and starting with the 2025.1 Vivado version, it seems that our main branch is not easily backwards compatible with older tools versions. 

What we suggest in this particular case would be to switch back to using Vivado 2025.1 for the HDL and when it comes to software we will discuss with someone from there to assist you if you encounter issues.

Hello, we are sorry for the long wait. We discussed this situation and starting with the 2025.1 Vivado version, it seems that our main branch is not easily backwards compatible with older tools versions. 

What we suggest in this particular case would be to switch back to using Vivado 2025.1 for the HDL and when it comes to software we will discuss with someone from there to assist you if you encounter issues.

Okay, I remove 23 and install work with 25 tool. I will post once I encounter problems with no-os

I removed 23 and installed 2025.1 tool

At the last steps design gives error. Seems timing constraints not met  Here is copy paste from log file. How to move forward?

open_run: Time (s): cpu = 00:00:34 ; elapsed = 00:00:34 . Memory (MB): peak = 4698.969 ; gain = 127.316
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
CRITICAL WARNING: [Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
report_timing_summary: Time (s): cpu = 00:00:44 ; elapsed = 00:00:25 . Memory (MB): peak = 4960.914 ; gain = 261.945
GENERATE_REPORTS: Resource utilization files won't be generated because ADI_GENERATE_UTILIZATION env var is not set
GENERATE_PORTS_REPORTS: IP ports properties and nets report files won't be generated because ADI_EXTRACT_PORTS env var is not set
GENERATE_REPORTS: Power analysis files won't be generated because ADI_GENERATE_XPA env var is not set
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -2, Temperature grade: E, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
INFO: [Project 1-1918] Creating Hardware Platform: c:/hdl/projects/adrv9026/zcu102/adrv9026_zcu102.sdk/system_top_bad_timing.xsa ...
INFO: [Project 1-1943] The Hardware Platform can be used for Hardware
INFO: [Project 1-1941] Successfully created Hardware Platform: c:/hdl/projects/adrv9026/zcu102/adrv9026_zcu102.sdk/system_top_bad_timing.xsa
INFO: [Hsi 55-2053] elapsed time for repository (C:/Xilinx/2025.1/Vivado/data/embeddedsw) loading 5 seconds
write_hw_platform: Time (s): cpu = 00:00:21 ; elapsed = 00:00:27 . Memory (MB): peak = 5527.395 ; gain = 552.809
ERROR: Timing Constraints NOT met!
while executing
"adi_project_run adrv9026_zcu102"
(file "system_project.tcl" line 66)
INFO: [Common 17-206] Exiting Vivado at Tue Nov 18 09:41:36 2025...

Hi, 

Please add the following lines under RX and ORX dma in adrv9026_bd.tcl:

ad_ip_parameter axi_adrv9026_rx_dma CONFIG.AXI_SLICE_DEST {true}
ad_ip_parameter axi_adrv9026_rx_dma CONFIG.AXI_SLICE_SRC {true}

and

ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.AXI_SLICE_DEST {true}
ad_ip_parameter axi_adrv9026_rx_os_dma CONFIG.AXI_SLICE_SRC {true}

From recent testing this seems to solve the timing issue.

Best regards,
Andrei

I rebuild with these. This has been taking alot of time so quick yes/no answers to these two questions are much appreciated from you:

1) I am working on this

projects/adrv9026/zcu102/system_project.tcl

I want to use RX observation path so in above tcl file do i need 

to set ORX_ENABLE          [get_env_param ORX_ENABLE         0 ]  to ORX_ENABLE=1
and last 4 parameters to these or they all should be as they are default in tcl?
 RX_OS_JESD_M=4 RX_OS_JESD_L=2 RX_OS_JESD_S=1 RX_OS_JESD_NP=16 RX_JESD_M=4 RX_JESD_L=2

2)  With ADRV9029 + ZCU102  as a first step I want to capture raw IQ data with and without DPD enabled can I do that with using Transceiver evaluation software (TES)? or there is more easier way to do this? Please help

With these corrections 2025.1 builds hdl..i still need to check if no-os works correctly with 2025.1 vitis

Hi,

1. You can just run the following and it will build the ORx support: ORx

2. TES doesn't work with ZCU102, it only works with ADS9-V2EBZ. Currently there is no DPD support in no-OS, but some work has been done on Linux. You can find it here

Best regards,
Andrei

Hello Socchiplet,

Do you have any updates? Have all the questions you had been answered?

Best regards,

Maria

Hi, Thank you for taking update. I need to figure out how to capture IQ data using DPD enable/disable for adrv9029 with ZCU102. It is disappointing to hear that example design and No-OS example does not contain any work relating to DPD although adrv9029 main feature is DPD. I need to study this and see how/what we can do. I will post new questions in a separate post later then.