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adrv9026 +ZCU102 HDL no-OS reference design (Vivado)

Thread Summary

The user inquired about the lack of ORx data support in the ADRV9026 + ZCU102 Vivado 2024.2 reference design. The final answer confirmed that ORx integration is nearly complete on the HDL side and will be tested with Linux, with no-OS support to follow. The user can use the ADS9-V2EBZ and TES for ORx evaluation in the meantime. The user also confirmed they will proceed with the ADRV9026/9029 + ZCU102 HDL no-OS reference design and asked if the ADRV9026-HB/PCBZ and ZCU102 are sufficient, to which the final answer did not provide a direct response.
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Category: Hardware
Product Number: adrv9026

I have successfully build and generated bit stream for adrv9026 +ZCU102 VIvado 2024.2 reference design

However, looking at the design I noticed there does not  seems to be  support for  Orx data to FPGA. Only Tx and Rx paths are there.

I can see that in another case you have answered like this almost 8 months ago:

"Currently, we don't have support for observation (Orx). It is work in progress, but we don't have a clear time-frame as to when it will be done."

This is very important for us. We are planning to order a couple of ADRV9026 platforms and we want to do some own work in FPGA relating to new DPD module while using your DPD as reference.

For us having access to ORx data in FPGA will help build our own design.  

i) Can you please tell when you can incorporate support for Orx data  in FPGA ?

ii) Can you please also tell what are other possibilities to get Orx data: Is is that there is some API which enables its transfer to (lets say a PC)?

Thansl

Parents
  • The issue here is that you are using the ignore version check as a build parameter, but it is an environment variable that needs to be exported separately. Please follow these instructions in your terminal:

    export ADI_IGNORE_VERSION_CHECK=1

    make

  • Could you also add the Error message? 

  • From log file

    ### ad_connect gpio_i sys_ps8/emio_gpio_i
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_i> is being overridden by the user with net <gpio_i_1>. This pin will not be connected as a part of interface connection <GPIO_0>.
    connect_bd_net /gpio_i /sys_ps8/emio_gpio_i
    ### ad_connect gpio_o sys_ps8/emio_gpio_o
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_o> is being overridden by the user with net <sys_ps8_emio_gpio_o>. This pin will not be connected as a part of interface connection <GPIO_0>.
    connect_bd_net /gpio_o /sys_ps8/emio_gpio_o
    ### ad_connect gpio_t sys_ps8/emio_gpio_t
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_gpio_t> is being overridden by the user with net <sys_ps8_emio_gpio_t>. This pin will not be connected as a part of interface connection <GPIO_0>.
    connect_bd_net /gpio_t /sys_ps8/emio_gpio_t
    ### ad_ip_instance ilconcat spi0_csn_concat
    WARNING: [Coretcl 2-175] No Catalog IPs found
    ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell spi0_csn_concat
    ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name spi0_csn_concat .
    ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
    "create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}"
    (procedure "ad_ip_instance" line 7)
    invoked from within
    "ad_ip_instance ilconcat spi0_csn_concat"
    (file "C:/hdl/projects/common/zcu102/zcu102_system_bd.tcl" line 112)

    while executing
    "source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl"
    (file "system_bd.tcl" line 10)

    while executing
    "source system_bd.tcl"
    (procedure "adi_project_create" line 136)
    invoked from within
    "adi_project_create $project_name $mode $parameter_list $device $board"
    (procedure "adi_project" line 80)
    invoked from within
    "adi_project adrv9026_zcu102 0 [list \
    JESD_MODE [get_env_param JESD_MODE 8B10B ] \
    ORX_ENABLE [get_env_param ORX_ENABLE ..."
    (file "system_project.tcl" line 37)
    INFO: [Common 17-206] Exiting Vivado at Fri Oct 31 11:16:02 2025...

  • Thank you. We'll reproduce this build and get back to you soon.

  • Hello  ,

    We reproduced this issue and it looks like we have a problem using the HDL main with the 2023.2 Vivado Version because of this change: Update utility cores to inline hdl variants · analogdevicesinc/hdl@eadd7d6.

    If you replace manually the ilconcat instances to xlconcat, everywhere in zcu102_system_bd.tcl, it should go past that error. 

  • I changed il to xl as you stated in the tcl file. Still fails. Here are some screen shots

    user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
    $ which vitis
    /cygdrive/c/Xilinx/Vitis/2023.2/bin/vitis

    user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
    $ which vivado
    /cygdrive/c/Xilinx/Vivado/2023.2/bin/vivado

    user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
    $ export ADI_IGNORE_VERSION_CHECK=1

    user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
    $ make
    Building axi_clkgen library [/cygdrive/c/hdl/library/axi_clkgen/axi_clkgen_ip.lo OK
    Building util_cdc library [/cygdrive/c/hdl/library/util_cdc/util_cdc_ip.log] ... OK
    Building util_axis_fifo library [/cygdrive/c/hdl/library/util_axis_fifo/util_axis_fifo_ip.log] ... OK
    Building axi_dmac library [/cygdrive/c/hdl/library/axi_dmac/axi_dmac_ip.log] ... OK
    Building axi_sysid library [/cygdrive/c/hdl/library/axi_sysid/axi_sysid_ip.log] ... OK
    Building interface definitions [/cygdrive/c/hdl/library/interfaces/interfaces_ip.log] ... OK
    Building util_axis_fifo_asym library [/cygdrive/c/hdl/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.log] ... OK
    Building data_offload library [/cygdrive/c/hdl/library/data_offload/data_offload_ip.log] ... OK
    Building ad_ip_jesd204_tpl_adc library [/cygdrive/c/hdl/library/jesd204/ad_ip_jesd204_tpl_adc/ad_ip_jesd204_tpl_adc_ip.log] ... OK
    Building ad_ip_jesd204_tpl_dac library [/cygdrive/c/hdl/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_ip.log] ... OK
    Building axi_jesd204_common library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_common/axi_jesd204_common_ip.log] ... OK
    Building axi_jesd204_rx library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_rx/axi_jesd204_rx_ip.log] ... OK
    Building axi_jesd204_tx library [/cygdrive/c/hdl/library/jesd204/axi_jesd204_tx/axi_jesd204_tx_ip.log] ... OK
    Building jesd204_common library [/cygdrive/c/hdl/library/jesd204/jesd204_common/jesd204_common_ip.log] ... OK
    Building jesd204_rx library [/cygdrive/c/hdl/library/jesd204/jesd204_rx/jesd204_rx_ip.log] ... OK
    Building jesd204_tx library [/cygdrive/c/hdl/library/jesd204/jesd204_tx/jesd204_tx_ip.log] ... OK
    Building sysid_rom library [/cygdrive/c/hdl/library/sysid_rom/sysid_rom_ip.log] ... OK
    Building util_do_ram library [/cygdrive/c/hdl/library/util_do_ram/util_do_ram_ip.log] ... OK
    Building util_hbm library [/cygdrive/c/hdl/library/util_hbm/util_hbm_ip.log] ... OK
    Building util_cpack2 library [/cygdrive/c/hdl/library/util_pack/util_cpack2/util_cpack2_ip.log] ... OK
    Building util_upack2 library [/cygdrive/c/hdl/library/util_pack/util_upack2/util_upack2_ip.log] ... OK
    Building axi_adxcvr library [/cygdrive/c/hdl/library/xilinx/axi_adxcvr/axi_adxcvr_ip.log] ... OK
    Building util_adxcvr library [/cygdrive/c/hdl/library/xilinx/util_adxcvr/util_adxcvr_ip.log] ... OK
    Building adrv9026_zcu102 project [/cygdrive/c/hdl/projects/adrv9026/zcu102/adrv9026_zcu102_vivado.log] ... FAILED
    For details see /cygdrive/c/hdl/projects/adrv9026/zcu102/adrv9026_zcu102_vivado.log

    make: *** [../../scripts/project-xilinx.mk:113: adrv9026_zcu102.sdk/system_top.xsa] Error 1

    user@MININT-3R5H5DV /cygdrive/c/hdl/projects/adrv9026/zcu102
    $

    detailed failure log

    ### ad_connect spi0_csn_concat/dout spi0_csn
    connect_bd_net /spi0_csn_concat/dout /spi0_csn
    ### ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_sclk_o> is being overridden by the user with net <sys_ps8_emio_spi0_sclk_o>. This pin will not be connected as a part of interface connection <SPI_0>.
    connect_bd_net /sys_ps8/emio_spi0_sclk_o /spi0_sclk
    ### ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_m_o> is being overridden by the user with net <sys_ps8_emio_spi0_m_o>. This pin will not be connected as a part of interface connection <SPI_0>.
    connect_bd_net /sys_ps8/emio_spi0_m_o /spi0_mosi
    ### ad_connect sys_ps8/emio_spi0_m_i spi0_miso
    WARNING: [BD 41-1306] The connection to interface pin </sys_ps8/emio_spi0_m_i> is being overridden by the user with net <spi0_miso_1>. This pin will not be connected as a part of interface connection <SPI_0>.
    connect_bd_net /sys_ps8/emio_spi0_m_i /spi0_miso
    ### ad_connect sys_ps8/emio_spi0_ss_i_n VCC
    WARNING: [Coretcl 2-175] No Catalog IPs found
    ERROR: [BD 41-74] Exec TCL: Please specify VLNV when creating IP cell VCC_1
    ERROR: [BD 5-7] Error: running create_bd_cell -type ip -name VCC_1 .
    ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
    "create_bd_cell -type ${ip_type} -vlnv ${ip_def} ${i_name}"
    (procedure "ad_ip_instance" line 7)
    invoked from within
    "ad_ip_instance ilconstant $cell_name"
    invoked from within
    "if {$cell eq ""} {
    # Create new constant source
    ad_ip_instance ilconstant $cell_name
    set cell [get_bd_cells -quiet $cell_name]
    set_pro..."
    (procedure "ad_connect_int_get_const" line 17)
    invoked from within
    "ad_connect_int_get_const $name_a $width"
    (procedure "ad_connect" line 84)
    invoked from within
    "ad_connect sys_ps8/emio_spi0_ss_i_n VCC"
    (file "C:/hdl/projects/common/zcu102/zcu102_system_bd.tcl" line 121)

    while executing
    "source $ad_hdl_dir/projects/common/zcu102/zcu102_system_bd.tcl"
    (file "system_bd.tcl" line 10)

    while executing
    "source system_bd.tcl"
    (procedure "adi_project_create" line 136)
    invoked from within
    "adi_project_create $project_name $mode $parameter_list $device $board"
    (procedure "adi_project" line 80)
    invoked from within
    "adi_project adrv9026_zcu102 0 [list \
    JESD_MODE [get_env_param JESD_MODE 8B10B ] \
    ORX_ENABLE [get_env_param ORX_ENABLE ..."
    (file "system_project.tcl" line 37)
    INFO: [Common 17-206] Exiting Vivado at Tue Nov 4 07:10:05 2025...

  • It would be great if you can provide input on this as still build fails. We are stuck at build stage. Thanks

  • It would be great if you can provide input on this as still build fails. We are stuck at build stage. Thanks

  • Hello, we are sorry for the long wait. We discussed this situation and starting with the 2025.1 Vivado version, it seems that our main branch is not easily backwards compatible with older tools versions. 

    What we suggest in this particular case would be to switch back to using Vivado 2025.1 for the HDL and when it comes to software we will discuss with someone from there to assist you if you encounter issues.

Reply
  • Hello, we are sorry for the long wait. We discussed this situation and starting with the 2025.1 Vivado version, it seems that our main branch is not easily backwards compatible with older tools versions. 

    What we suggest in this particular case would be to switch back to using Vivado 2025.1 for the HDL and when it comes to software we will discuss with someone from there to assist you if you encounter issues.

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