Category: Software
Product Number: AD9207
Software Version: Petalinux-v2023.2
Dear ADI EngineerZone Support Team,
We are facing a significant issue with the AD9207 dual ADC integrated on our custom board, which utilizes a Zynq Ultrascale+ ZU11EG platform. We are using the IIO Oscilloscope application for initial validation.
Problem Description:
Currently, we are only able to observe valid data on the voltage0 channel (ADC0) of the AD9207. The voltage1 channel (ADC1) consistently shows a flat line in the IIO Oscilloscope.
Furthermore, when we attempt to capture data specifically from voltage1 using iio_readdev, the output file contains no meaningful data (all zeros).
Debugging Steps and Observations:
To diagnose this, we have utilized ILA probe at the output of the axi_mxfe_rx_jesd IP core. This analysis reveals that only the lower 256 bits (bit indices 0 to 255) of the expected 512-bit data bus are active.
It appears that the complete 512-bit JESD data is not being correctly processed or forwarded by the axi_mxfe_rx_jesd IP to the subsequent rx_mxfe_tpl_core. This bottleneck seems to be the reason why only adc_data_0 (corresponding to voltage0) is valid, while adc_data_1 remains inactive.
Additionally, we have tapped all 8 JESD lanes originating from the util_mxfe_xcvr IP core, which feeds into the axi_mxfe_rx_jesd IP. The ILA probes on these lanes indicate that data (64bit each) is being received across all eight lanes by the axi_mxfe_rx_jesd IP.
device tree,
/ {
fpga_axi: fpga-axi@0 {
interrupt-parent = <&gic>;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;
rx_dma: dma@9c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c420000 0x0400>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 73>;
};
axi_ad9081_core_rx: axi-ad9081-rx-hpc@84a10000 {
compatible = "adi,axi-ad9081-rx-1.0";
reg = <0x84a10000 0x2000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&trx0_ad9081>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
};
axi_ad9081_rx_jesd: axi-jesd204-rx@84a90000 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x84a90000 0x4000>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 71>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 1>, <&axi_ad9081_adxcvr_rx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_adxcvr_rx 0 FRAMER_LINK0_RX>;
};
axi_ad9081_adxcvr_rx: axi-adxcvr-rx@84a60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,axi-adxcvr-1.0";
reg = <0x84a60000 0x10000>;
clocks = <&hmc7044 12>;
clock-names = "conv";
#clock-cells = <1>;
clock-output-names = "rx_gt_clk", "rx_out_clk";
adi,sys-clk-select = <XCVR_QPLL1>;
adi,out-clk-select = <XCVR_PROGDIV_CLK>;
adi,use-lpm-enable;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
};
axi_sysid_0: axi-sysid-0@85000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x85000000 0x10000>;
};
axi_data_offload_rx: axi-data-offload-1@9c450000 {
compatible = "adi,axi-data-offload-1.0.a";
reg = <0x9c450000 0x4000>;
};
};
};
&spi1 {
status = "okay";
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2343750>; /* 2 MHz */
/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/
adi,pll1-clkin-frequencies = <100000000 100000000 0 0>;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll2-output-frequency = <2400000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <16>; // 150 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <1536>; // 0.78125 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <16>; // 150 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c10: channel@a {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <16>; // 150 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c12: channel@c {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <16>; // 150 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c13: channel@d {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <1536>; // 0.78125 MHz
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
adi,jesd204-sysref-chan;
//adi,disable;
};
};
};
&spi0 {
status = "okay";
trx0_ad9081: ad9082@0 {
reset-gpios = <&gpio 133 0>;
sysref-req-gpios = <&gpio 121 0>;
rx2-enable-gpios = <&gpio 135 0>;
rx1-enable-gpios = <&gpio 134 0>;
//tx2-enable-gpios = <&gpio 137 0>;
//tx1-enable-gpios = <&gpio 136 0>;
#address-cells = <1>;
#size-cells = <0>;
//compatible = "adi,ad9082";
compatible = "adi,ad9207";
reg = <0>;
spi-max-frequency = <1000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX>;
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>;
adi,continuous-sysref-mode-disable;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <9600000000>;
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <4800000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_ZIF>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_I>;
adi,logical-lane-mapping = /bits/ 8 <0 1 2 3 4 5 6 7>;
adi,link-mode = <19>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <2>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <2>; /* JESD M */
adi,octets-per-frame = <1>; /* JESD F */
adi,frames-per-multiframe = <256>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <8>; /* JESD L */
adi,samples-per-converter-per-frame = <2>; /* JESD S */
adi,high-density = <1>; /* JESD HD */
};
};
};
};
};
- Could this issue be related to an incorrect configuration of the
axi_mxfe_rx_jesdIP core? Are there specific parameters or settings within this IP that could cause it to process only half of the incoming JESD data? - Is there a known limitation or configuration requirement regarding the data bus width or lane aggregation within the
axi_mxfe_rx_jesdIP when interfacing with the AD9207 in a dual-channel configuration? - Could the device tree configuration be contributing to this problem? Are there any specific properties related to the
axi_mxfe_rx_jesdor the AD9207 node that we should examine or modify?
Could you please provide any insights or guidance to resolve this issue and enable data acquisition on both ADC channels. I can provide more details if you want to check.
Thank you for your time and support.
