JESD LMFC calculation on FPGA Rx side

Hi,

I presume you're talking about the AD9083_EVB HDL project, right?

Can you tell me the values you set for the JESD parameters?

Best regards,
Iulia

Hello Iulia

Thanks

We used the evb project as the reference, but it is not supporting sysref, so we had move to our PCB.

I am attaching the configuration in the dtsi. It is working well for subclass 0, but when changing to subclass 1 AD9083 seems to be satisfied with the sysref pulses (according to status register), but the lane is not working.

1. I wonder why changing multi fame number between 32 and 16 doesn't affect the LMFC calculation (always ~390KHz).

2. I try k divider values of 128, 256 and 512 but it doesn't impact.

	    adc0_ad9083: ad9083@0 {
	        compatible = "adi,ad9083";
	        reg = <0>;
	        
	        jesd204-device;
	        #jesd204-cells = <2>;
	        jesd204-top-device = <0>;
	        jesd204-link-ids = <0>;
	        jesd204-inputs = <&rx_ad9083_tpl_core_adc_tpl_core 0 0>;
	 
	        spi-max-frequency = <1000000>;
	        //clocks = <&ad9528 13>;
	        //clock-names = "adc_ref_clk";
	        clocks = <&ad9528 2>;
	        clock-names = "adc_ref_clk";
	        adi,adc-frequency-hz= /bits/ 64 <1600000000>; /* 1.6 GHz */
	 
	        /* adi_ad9083 config */
	 
	        adi,vmax-microvolt = <1800>;
	        adi,fc-hz =  /bits/ 64 <125000000>;
	        adi,rterm-ohms = <100>;
	        adi,backoff = <0>;
	        adi,finmax-hz = /bits/ 64 <80000000>;
	        adi,nco0_freq-hz = /bits/ 64 <10156250>;
	        adi,nco1_freq-hz = /bits/ 64 <0>;
	        adi,nco2_freq-hz = /bits/ 64 <0>;
	        adi,cic_decimation = /bits/ 8 <2>; /* AD9083_CIC_DEC_16 */
	        adi,j_decimation = /bits/ 8 <3>; /* AD9083_J_DEC_16 */
	        adi,g_decimation = /bits/ 8 <0>;
	        adi,h_decimation = /bits/ 8 <0>;
	        adi,nco0_datapath_mode = /bits/ 8 <2>; /* AD9083_DATAPATH_ADC_CIC_NCO_J */
	 
	        /* JESD204 parameters */
	 
	        adi,octets-per-frame = <64>;
	        adi,frames-per-multiframe = <16>;
	        adi,converter-resolution = <16>;
	        adi,bits-per-sample = <16>;
	        adi,converters-per-device = <32>;
	        adi,control-bits-per-sample = <0>;
	        adi,lanes-per-device = <1>;
	        adi,subclass = <1>;
          	adi,jesd204-framer-a-lmfc-offset = <15>;

	        /* software reset, resistor is not mounted */
	            /* reset-gpios = <&gpio 111 0>; */
	            pwdn-gpios = <&gpio 110 0>;
	    };

	    ad9528_1: ad9528@1 {
	        compatible = "adi,ad9528";
	        reg = <1>;
                label = "sysref_source";
	        //spi-cpol;
	        //spi-cpha;
	        #address-cells = <1>;
	        #size-cells = <0>;
	
	        jesd204-device;
	        #jesd204-cells = <2>;
	        //jesd204-inputs = <&ad9528 0 0>;
  	        jesd204-sysref-provider;
	        spi-max-frequency = <1000000>;
	        adi,spi-3wire-enable;
	
	        clock-output-names = "ad9528-2_out0", "ad9528-2_out1", "ad9528-2_out2",
	            "ad9528-2_out3", "ad9528-2_out4", "ad9528-2_out5", "ad9528-2_out6",
	            "ad9528-2_out7", "ad9528-2_out8", "ad9528-2_out9", "ad9528-2_out10",
	            "ad9528-2_out11", "ad9528-2_out12", "ad9528-2_out13";
	        #clock-cells = <1>;
	        
	        adi,vcxo-freq = <100000000>;
	
	        adi,refa-enable;
	        adi,refa-diff-rcv-enable;
	        adi,refa-r-div = <1>;
	        /*adi,osc-in-cmos-neg-inp-enable;*/
	        
	        adi,sysref-src = <2>; /* SYSREF_SRC_INTERNAL */
	        adi,sysref-pattern-mode = <0>; /* SYSREF_PATTERN_NSHOT */
	        adi,sysref-k-div = <256>;
	        adi,sysref-nshot-mode = <3>; /* SYSREF_NSHOT_4_PULSES */
	        adi,sysref-request-trigger-mode = <0>; /* SYSREF_LEVEL_HIGH */
	        adi,jesd204-max-sysref-frequency-hz = <400000>;
    
	        /* PLL1 config */
	        adi,pll1-feedback-src-vcxo;
	        adi,pll1-feedback-div = <4>;
	        adi,pll1-charge-pump-current-nA = <5000>;
	        /* adi,osc-in-diff-enable;*/
    
	        /* PLL2 config */
	        /*
	         * Valid ranges based on VCO locking range:
	         *   1150.000 MHz - 1341.666 MHz
	         *    862.500 MHz - 1006.250 MHz
	         *    690.000 MHz -  805.000 MHz
	         */
	        adi,pll2-m1-frequency = <1000000000>;
	        adi,pll2-charge-pump-current-nA = <805000>;
	
	        adi,rpole2 = <0>; /* RPOLE2_900_OHM */
	        adi,rzero = <7>; /* RZERO_1850_OHM */
	        adi,cpole1 = <2>; /* CPOLE1_16_PF */
	
	        adi,status-mon-pin0-function-select = <0xFF>; /* No function */
	        adi,status-mon-pin1-function-select = <0xFF>; /* No function */
	

	        ad9528_1_c0: channel@0 {
	            reg = <0>;
	            adi,extended-name = "SXB0_2_SYSREF";
	            adi,driver-mode = <0>; /* DRIVER_MODE_LVDS */
	            adi,divider-phase = <0>;
	            adi,channel-divider = <10>; /* 100 MHz */
	            adi,signal-source = <2>; /* SOURCE_SYSREF_VCO */
	        };

                ad9528_1_c1: channel@1 {
	            reg = <1>;
	            adi,extended-name = "SYB2_1_SYSREF";
	            adi,driver-mode = <0>; /* DRIVER_MODE_LVDS */
	            adi,divider-phase = <0>;
	            adi,channel-divider = <10>; /* 100 MHz */
	            adi,signal-source = <2>; /* SOURCE_SYSREF_VCO */
	        };

/ {
	clocks {
		rx_fixed_link_clk: clock@1 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <100000000>;
			clock-output-names = "rx_link_clk";
		};
	};
};

	// axi_dmac@9c400000 
	&axi_ad9083_rx_dma {
			compatible = "adi,axi-dmac-1.00.a";
			#dma-cells = <1>;
			#clock-cells = <0>;
	};
	
	// ad_ip_jesd204_tpl_adc@84a00000
	&rx_ad9083_tpl_core_adc_tpl_core {
			compatible = "adi,axi-ad9083-rx-1.0";
			dmas = <&axi_ad9083_rx_dma 0>;
			dma-names = "rx";
			spibus-connected = <&adc0_ad9083>;
	
			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9083_rx_jesd_rx_axi 0 0>;
	};
	
	// axi_jesd204_rx@84aa0000
	&axi_ad9083_rx_jesd_rx_axi {
			compatible = "adi,axi-jesd204-rx-1.0";
			clocks = <&zynqmp_clk 71>, <&ad9528 4>, <&axi_ad9083_rx_xcvr 0>, <&rx_fixed_link_clk>;
			clock-names = "s_axi_aclk", "device_clk", "lane_clk", "link_clk";

			#clock-cells = <0>;
			clock-output-names = "jesd_rx_lane_clk";

			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&axi_ad9083_rx_xcvr 0 0>;
	};

	// axi_adxcvr@84a60000
	&axi_ad9083_rx_xcvr {
	        compatible = "adi,axi-adxcvr-1.0";
			clocks = <&zynqmp_clk 71>, <&ad9528 9>;
			clock-names = "s_axi_aclk", "conv";
	
			#clock-cells = <1>;
			clock-output-names = "rx_gt_clk", "rx_out_clk";

			adi,sys-clk-select = <2>; // XCVR_QPLL1
			adi,out-clk-select = <3>; // XCVR_REFCLK
			adi,use-lpm-enable;
			jesd204-device;
			#jesd204-cells = <2>;
			jesd204-inputs = <&ad9528 0 0>;
	};

	// axi_sysid@85000000
	&axi_sysid_0 {
			compatible = "adi,axi-sysid-1.00.a";
	};
	

Regards

Hi,

NRW said:

We used the evb project as the reference, but it is not supporting sysref, so we had move to our PCB.

Is the screenshot from when using your PCB? The device clock being so low as 6.25MHz, raises some questions.

What is your desired lane rate? Which JESD mode did you choose? You can't pick the values as you wish, they need to be from the supported combinations. I see you didn't set a value for S parameter.

Regarding LMFC, I think (though I'm not 100% sure yet) it has a relationship between F*K, to be a multiple of 4 and to be somewhere between [20; 256] if I remember correctly. As to why it is not changing, it may be because the F*K you're keeping constant, is it? Also K I think it should be <= 256, but you should check in the data sheet. F is calculated with a formula as well, it is a function of M, NP, S and L, I don't have it right now in mind, you should find it with a quick search.

Best regards,
Iulia

Indeed the screenshot is from my PCB, wonder why the 6.25MHz raise some questions?
I am using S =1, it is defined in the parameters for the BD. 
I missed the part that it has to be a mutiple of 4, I didn't see that. This might explain why I always get 390 KHz for LMFC rate. 
Why K has to be less than 512? 
I manage to lock on the sysref after changing the AD9083 configuration following "Engineer_Note_AD9083 SYSREF Interface with LVDS" document.

Thanks  

Hi,

We are trying to reproduce the setup you have, on a ZCU102 in Subclass 0, though.

Looking over the data sheet, it seems that in some modes the JESD K parameter is restricted to 16. From Tables 24, 25, could you tell me the exact mode you're using?

6.25MHz is atypical for us because we usually use the maximum bandwidth for devices and typical devices have M=2->8. But in this situation it should be fine.

Best regards,
Iulia

We could reproduce your setup and the values shown in jesd_status.

The LMFC is not changing because K in this mode, is limited to 16 so it can't change to 32.

Thank you