Category: Software
Product Number: AD9081
Software Version: Petalinıx 2022.2
Hello everyone,
I am developing a Linux based application using AD9081 and ZCU102. I compiled a kernel using the xsa file I received with the reference HDL design (dafault). Everything is as it should be but I am getting an error in ad9081 spi1.0. dmseg messages are as follows;
ad9081 spi1.0: supply vdd not found, using dummy regulator ad9081 spi1.0:PLL not locked, "pll_lock" in adi_ad9081_device_clk_pll_div_set(...), line 402 in drivers/iio/adc/ad9081/adi_ad9081_device.c ad9081 spi1.0:Failed to initialize: -21 ad9081: probe of spi1.0 failed with error -21
Because this is the case, ad9081 does not appear as a device under iio.
The dtsi files I used are as follows.
https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/adi-ad9081-fmc-ebz.dtsi
I couldn't understand what the problem was. In addition the output of the " iio_attr -D hmc7044 status " message is as follows.
- - - PLL1 - - - Status : Locked Using : CLKIN0 @ 100000000 Hz PFD: 1000 kHz - - - PLL2 - - - Status : Unlocked(Synchronized) Frequency : 300000000 Hz(Autocal cap bank value:16) SYSREF Status: Invalid SYNC Status : Unsynchronized Lock Status: Unlocked
system-user.dtsi file
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD9081-FMC-EBZ
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
* https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl
*
* Copyright (C) 2019-2020 Analog Devices Inc.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
#include <dt-bindings/jesd204/adxcvr.h>
&i2c1 {
i2c-mux@75 {
i2c@0 { /* HPC0 */
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
/* HPC0_IIC */
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
};
};
@qspi
{
flash@0
{
compatible = "m25p80", "jedec,spi-nor";
reg = <0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;
spi-max-freqency = <20000000>;
}
}
/ {
fpga_axi: fpga-axi@0 {
interrupt-parent = <&gic>;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;
rx_dma: dma@9c420000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c420000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 73>;
};
tx_dma: dma@9c430000 {
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c430000 0x10000>;
#dma-cells = <1>;
#clock-cells = <0>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 73>;
};
axi_ad9081_core_rx: axi-ad9081-rx-hpc@84a10000 {
compatible = "adi,axi-ad9081-rx-1.0";
reg = <0x84a10000 0x8000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&trx0_ad9081>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_rx_jesd 0 FRAMER_LINK0_RX>;
};
axi_ad9081_core_tx: axi-ad9081-tx-hpc@84b10000 {
compatible = "adi,axi-ad9081-tx-1.0";
reg = <0x84b10000 0x4000>;
dmas = <&tx_dma 0>;
dma-names = "tx";
clocks = <&trx0_ad9081 1>;
clock-names = "sampl_clk";
spibus-connected = <&trx0_ad9081>;
//adi,axi-pl-fifo-enable;
adi,axi-data-offload-connected = <&axi_data_offload_tx>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_tx_jesd 0 DEFRAMER_LINK0_TX>;
};
axi_ad9081_rx_jesd: axi-jesd204-rx@84a90000 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x84a90000 0x1000>;
interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 71>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_adxcvr_rx 0 FRAMER_LINK0_RX>;
};
axi_ad9081_tx_jesd: axi-jesd204-tx@84b90000 {
compatible = "adi,axi-jesd204-tx-1.0";
reg = <0x84b90000 0x1000>;
interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
#clock-cells = <0>;
clock-output-names = "jesd_tx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9081_adxcvr_tx 0 DEFRAMER_LINK0_TX>;
};
axi_ad9081_adxcvr_rx: axi-adxcvr-rx@84a60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,axi-adxcvr-1.0";
reg = <0x84a60000 0x1000>;
clocks = <&hmc7044 12>;
clock-names = "conv";
#clock-cells = <1>;
clock-output-names = "rx_gt_clk", "rx_out_clk";
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_REFCLK_DIV2>;
adi,use-lpm-enable;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&hmc7044 0 FRAMER_LINK0_RX>;
};
axi_ad9081_adxcvr_tx: axi-adxcvr-tx@84b60000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,axi-adxcvr-1.0";
reg = <0x84b60000 0x1000>;
clocks = <&hmc7044 12>;
clock-names = "conv";
#clock-cells = <1>;
clock-output-names = "tx_gt_clk", "tx_out_clk";
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_REFCLK_DIV2>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK0_TX>;
};
axi_sysid_0: axi-sysid-0@85000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x85000000 0x10000>;
};
axi_data_offload_tx: axi-data-offload-0@9c440000 {
compatible = "adi,axi-data-offload-1.0.a";
reg = <0x9c440000 0x10000>;
// adi,bringup;
// adi,oneshot;
// adi,bypass;
// adi,sync-config = <2>;
// adi,transfer-length = /bits/ 64 <0x10000>; // 2**16 bytes
};
axi_data_offload_rx: axi-data-offload-1@9c450000 {
compatible = "adi,axi-data-offload-1.0.a";
reg = <0x9c450000 0x10000>;
};
};
};
&spi0 {
status = "okay";
};
#define fmc_spi spi0
#include "ad9081-device.dtsi"
// ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
// .dio_t (gpio_t[43:32]),
// .dio_i (gpio_o[43:32]),
// .dio_o (gpio_i[43:32]),
// dio_p ({hmc_gpio1, // 43 121
// gpio[10:0]})); // 42-32
//
// assign gpio_i[44] = agc0[0];
// assign gpio_i[45] = agc0[1];
// assign gpio_i[46] = agc1[0];
// assign gpio_i[47] = agc1[1];
// assign gpio_i[48] = agc2[0];
// assign gpio_i[49] = agc2[1];
// assign gpio_i[50] = agc3[0];
// assign gpio_i[51] = agc3[1];
// assign gpio_i[52] = irqb[0];
// assign gpio_i[53] = irqb[1];
//
// assign hmc_sync = gpio_o[54];
// assign rstb = gpio_o[55]; 133
// assign rxen[0] = gpio_o[56]; 134
// assign rxen[1] = gpio_o[57]; 135
// assign txen[0] = gpio_o[58]; 136
// assign txen[1] = gpio_o[59]; 137
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
reset-gpios = <&gpio 133 0>;
sysref-req-gpios = <&gpio 121 0>;
rx2-enable-gpios = <&gpio 135 0>;
rx1-enable-gpios = <&gpio 134 0>;
tx2-enable-gpios = <&gpio 137 0>;
tx1-enable-gpios = <&gpio 136 0>;
};
};
ad9081-device.dtsi file
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD9081-FMC-EBZ on Xilinx ZynqMP ZCU102 Rev 1.0
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
* https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl
*
* Copyright (C) 2019-2020 Analog Devices Inc.
*/
#include <dt-bindings/iio/frequency/hmc7044.h>
#include <dt-bindings/iio/adc/adi,ad9081.h>
/delete-node/ &axi_mxfe_rx_dma;
/delete-node/ &axi_mxfe_rx_jesd_rx_axi;
/delete-node/ &misc_clk_0;
/delete-node/ &axi_mxfe_rx_xcvr;
/delete-node/ &axi_mxfe_tx_dma;
/delete-node/ &axi_mxfe_tx_jesd_tx_axi;
/delete-node/ &axi_mxfe_tx_xcvr;
/delete-node/ &axi_sysid_0;
/delete-node/ &mxfe_rx_data_offload_i_data_offload;
/delete-node/ &mxfe_tx_data_offload_i_data_offload;
/delete-node/ &rx_mxfe_tpl_core_adc_tpl_core;
/delete-node/ &tx_mxfe_tpl_core_dac_tpl_core;
/*
* VCXO = 122.880 MHz, XO = 122.880 MHz (AD9081-FMC-EBZ)
*/
&spi1 {
status = "okay";
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/
//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
//adi,vcxo-frequency = <122880000>;
adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll1-charge-pump-current-ua = <720>;
adi,pfd1-maximum-limit-frequency-hz = <1000000>; /* 1 MHz */
adi,pll2-output-frequency = <3000000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c0: channel@0 {
reg = <0>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c2: channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c3: channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <1536>; // 1.953125
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
hmc7044_c6: channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c8: channel@8 {
reg = <8>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c10: channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c12: channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <12>; // 250
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
};
hmc7044_c13: channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <1536>; // 1.953125
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>; // LVDS
adi,jesd204-sysref-chan;
};
};
};
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <12000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <6>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,crossbar-select = <&ad9081_tx_fddc_chan0>;
adi,nco-frequency-shift-hz = /bits/ 64 <1000000000>; /* 1000 MHz */
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,crossbar-select = <&ad9081_tx_fddc_chan1>;
adi,nco-frequency-shift-hz = /bits/ 64 <1100000000>; /* 1100 MHz */
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,crossbar-select = <&ad9081_tx_fddc_chan2>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1200000000>; /* 1200 MHz */
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,crossbar-select = <&ad9081_tx_fddc_chan3>; /* All 4 channels @ dac2 */
adi,nco-frequency-shift-hz = /bits/ 64 <1300000000>; /* 1300 MHz */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <8>;
ad9081_tx_fddc_chan0: channel@0 {
reg = <0>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan1: channel@1 {
reg = <1>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan2: channel@2 {
reg = <2>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_tx_fddc_chan3: channel@3 {
reg = <3>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>;
adi,link-mode = <9>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <4000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0: adc@0 {
reg = <0>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <400000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc1: adc@1 {
reg = <1>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <(-400000000)>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc2: adc@2 {
reg = <2>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
ad9081_adc3: adc@3 {
reg = <3>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <100000000>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0: channel@0 {
reg = <0>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan1: channel@1 {
reg = <1>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan4: channel@4 {
reg = <4>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_rx_fddc_chan5: channel@5 {
reg = <5>;
adi,decimation = <4>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>,
<&ad9081_rx_fddc_chan1 FDDC_I>, <&ad9081_rx_fddc_chan1 FDDC_Q>,
<&ad9081_rx_fddc_chan4 FDDC_I>, <&ad9081_rx_fddc_chan4 FDDC_Q>,
<&ad9081_rx_fddc_chan5 FDDC_I>, <&ad9081_rx_fddc_chan5 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>;
adi,link-mode = <10>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <8>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
};
};
Note: Additionally, when I try with non-OS I get the same error code.
Sincelery
No-Os result
[edited by: FarukS at 5:44 PM (GMT -5) on 4 Nov 2024]
