A customer found in the below github project for AD9081 what they describe as a TCL error.
https://github.com/analogdevicesinc/hdl/tree/main/projects/ad9081_fmca_ebz/vpk180
They said: “It incorrectly rounds values as part of the JESD project build script.
Changing the versal_transceiver.tcl script as follows fixes the problem
- set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000 / ${clk_divider}]]
- set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000 / ${clk_divider}]]
+ set rx_progdiv_clock [format %.3f [expr $rx_lane_rate * 1000.000 / ${clk_divider}]]
+ set tx_progdiv_clock [format %.3f [expr $tx_lane_rate * 1000.000 / ${clk_divider}]]
The prior code incorrectly changed 333.333 MHz to 333.000 MHz, which isn’t compatible with the other design parameters.”
