Hi yuanciou,

From the log that you provided:

ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". If you are using a license server, verify that the license server is up and running a version of the xilinx daemon that is compatible with the version of Xilinx software that you are using. Note: Vivado 2021.1 and later versions require upgrading your license server tools to the Flex 11.17.2.0 versions. Please confirm with your license admin that the correct version of the license server tools are installed.

So the issue is with your ZC706 license. Please check the Vivado License Manager and make sure that there is a valid ZC706 license there.

Regards,

Bogdan

Hi yuanciou,

From the log that you provided:

ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". If you are using a license server, verify that the license server is up and running a version of the xilinx daemon that is compatible with the version of Xilinx software that you are using. Note: Vivado 2021.1 and later versions require upgrading your license server tools to the Flex 11.17.2.0 versions. Please confirm with your license admin that the correct version of the license server tools are installed.

So the issue is with your ZC706 license. Please check the Vivado License Manager and make sure that there is a valid ZC706 license there.

Regards,

Bogdan

Hi sir : 

The previous license problem was solved.

I do the make ADI Project HDL again.

The flow stop at Building daq2_zc706 project [/home/pam/xilinx/adi/hdl/projects/daq2/zc706/daq2_zc706_vivado.log] ... FAILED . like picture 1 .

and the log information at below.

How do I solve the error?

The error : 

picture 1 : 

log file : 

4667.daq2_zc706_vivado.log

Did you do any changes to the code?

The log file doesn't tell me much about the error. If you open the project by running vivado *.xpr & 
you will get more information on it.

Hi iulia : 

I don't change the code. beside I don't have  ZC706+AD9081 project code.

I want to get ADI : ZC706+AD9081 source code project.

I follow the ADI Website(https://analogdevicesinc.github.io/hdl/user_guide/build_hdl.html) Build an HDL project

and the picture 1 is that I do follow ADI website instruction.

I build the project in Linux.

Do I do the right way?

picture 1 : 

Seems to be the proper way (but you are building daq2, not ad9081, if you want to build the ad9081 you have to run the make command from hdl/projects/ad9081_fmca_ebz/zc706), can you share the `/home/pam/xilinx/adi/hdl/projects/daq2/zc706/daq2_zc706.runs/system_axi_ddr_cntrl_0_synth_1/runme.log` log so I can see exactly what synthesis error pops up?

Thanks,

Bogdan

Hi bluncan : 

(1) Here is the log file, from /home/pam/xilinx/adi/hdl/projects/daq2/zc706/daq2_zc706.runs/system_axi_ddr_cntrl_0_synth_1/runme.log

(2) you mean I have to  do make at the path is /home/pam/xilinx/adi/hdl/projects/ad9081_fmca_ebz , not at /home/pam/xilinx/adi/hdl/projects ?

084162.runme.log

Hi!

It seems like the process that is doing the synthesis of the axi_ddr component crashes:

/tools/Xilinx/Vivado/2023.2/bin/rdiArgs.sh: line 369: 16573 Killed  
"$RDI_PROG" "$@"Parent process (pid 16573) has died. This helper process will now exit

How much RAM and disk space does your build machine have?

For your second question, yes, the hdl projects structure is like this: ADI_PART/FPGA_CARRIER, so if you want to build an ad9081 design for the ZC706 you have to build (run the 'make' command) inside the 'hdl/projects/ad9081_fmca_ebz/zc706' folder.

Regards,

Bogdan

Hi bluncan : 

1.  RAM : 10G , disk :1T 

Would it be occupied much resource in memory ? 

2. I will try do make in 'hdl/projects/ad9081_fmca_ebz/zc706' folder.

I think you need at least 16 gb of ram to build those designs, you could try to increase the 'swap' memory and see if it builds that way.

Regards,

Bogdan

Hi bluncan : 

The picture 1 is building path (xilinx/adi/hdl/projects/ad9081_fmca_ebz/zc706) . 

it doesn't show any failed message.

So is it building HDL file (zc706+ad9081) process correct?

I got the HDL source filed?

picture 1 : 

log : 

ad9081_fmca_ebz_zc706_vivado.log

Hi yuanciou,

Yes that looks okay, you should find the built .xsa in 'hdl/projects/ad9081_fmca_ebz/zc706/ad9081_fmca_ebz_zc706.sdk'.

You can also find the steps to boot the board here: https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynq

Regards,

Bogdan