FMCOOMS5 external clock

Yes, correct. You have to remove C348 as well along with R360, as C348 shares the same pad with C301

Thank you for the reply. That part is already done. Now I need help regarding the external clock ratings. I bought the AST3TQ- T-50-40MHz-C (datasheet -> AST3TQ-50 (mouser.com)) and AST3TQ-Eval. Is the output of this oscillator ok to use? In FMComms5 Configuration Options [Analog Devices Wiki] it says that "The level of the external reference should be ensured to not exceed the ADCLK846 input conditions (1.8 V p-p), and it will still be used to distribute the reference clock to the two AD9361s.". But in the datasheet of AST3TQ I only get that VOL_max=0.4V and VOH_min=2.4 which I do not know how to properly compare with Vpp.

But according to  FMComms5 Configuration Options [Analog Devices Wiki J301 drives  ADCLK846 which can receiver 1.8Vpp. In this way I should be able to connect the signa since from my measurements, when supplying 3.3V to AST3TQ-50 I get ~1.7 Vpp. Is that rigth?

If you are getting 1.7Vp-p at the output of the clock chip, that you have selected, then you can connect that to the  ADCLK846  input, that receives 1.8Vp-p. You can also manually probe and check the voltage levels at the  XTALN pin for confirmation.

Thank you for the help! I will move now to the device tree topic and hopefully everything works fine!

I have been trying to find the device tree file that I need to change but I am not being able to... I am using petalinux to generate the image with the meta-adi workflow (version 2022.2). Where should I make the changes? From what I managed to find I should add "adi,xo-disable-use-ext-refclk-enable" to each ad9361 and change the clock as follows:

Yes your understanding is correct.

I did manage to change it in the system-user.dtsi of petalinux. My device boots fine and I can even use iio-osciloscope to check signals. Is there any command I can use to check the integrity of the chips functionality? Because I am using them for GPS tracking, and when I use a pre-recorded file everything is fine, but as soon as I start using the ADCs' data it stops to work

Diogo said:

but as soon as I start using the ADCs' data it stops to work

What do you mean by this? Are you trying to use data capture in continuous mode? can you explain in detail?

So, I am trying to implement a GPS receiver by using the FMCOMMS5+ZCU102. For that I am using the reference design from ADi and added my custom modules. I am getting the data from the ADCs from the util_ad9361_adc_fifo. When doing this way I can do the acquisition of the GPS signals, but I cannot get the tracking to work... To make sure it was not an issue with my tracking module I loaded a BRAM with pre-recorded data (with USRP N210) and the module works fine. I seems like the samples are not properly getting into my modules. Am I getting them from the proper ADi IP? Other question is, how can I make sure that the front-end is properly configured for GPS signals?

Moving to FPGA reference designs forum for questions on this IP

Yes, util_ad9361_adc_fifo is the typical point to insert IP. Here to get 1 sample per clock at the sample rate of the device.

Properly configuring the transceiver would likely be more dependent on your GPS receiver IP configuration. I would perform a data capture with FMComms5 and run it through your IP in simulation to more easily understand where your receiver IP has a mismatch with data coming from the transceiver.

-Travis

Yes, util_ad9361_adc_fifo is the typical point to insert IP. Here to get 1 sample per clock at the sample rate of the device.

Properly configuring the transceiver would likely be more dependent on your GPS receiver IP configuration. I would perform a data capture with FMComms5 and run it through your IP in simulation to more easily understand where your receiver IP has a mismatch with data coming from the transceiver.

-Travis