AD9208
Recommended for New Designs
The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-
hold circuit designed for low...
Datasheet
AD9208 on Analog.com
AD9695
Recommended for New Designs
The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed...
Datasheet
AD9695 on Analog.com
manuals
Obsolete
Datasheet
manuals on Analog.com
AD9689
Recommended for New Designs
The AD9689 is a dual, 14-bit, 2.0 GSPS/2.6 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and-hold circuit designed...
Datasheet
AD9689 on Analog.com
this is my bring up procedure for the ad9695-625 board based on the ad9695_fmc example hdl. I had a terrible time figuring this out. there are lots of gotchas and caveats that are not apparent in the procedure. im not covering every step, but will provide my modified source material examples so it can be constructed and understood. there may be some rambling here...
tips
#user configuration
#OE TERMINAL=”tmux”
KERNAL_DTB=”my_ad9695”
The build will fail with two failures no file found and cannont find “pl-delete-note-my_ad9695.dtsi”
petalinux-build
that should pass
Here are other commands to build components of linux
mmc rescan
mmc part
fatload mmc 0:1 0x100000 BOOT.BIN
fatload mmc 0:1 0x2A00000 system.dtb
fatload mmc 0:1 0x3000000 Image
setenv bootargs 'console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1'
booti 0x3000000 - 0x2A00000
here are snippets of interest from the boot log:
[ 3.647116] axi_adxcvr 84a60000.axi-adxcvr-rx: AXI-ADXCVR-RX (17.05.a) using QPLL on GTH4 at 0x84A60000. Number of lanes: 4.
[ 3.657490] axi-jesd204-rx 84aa0000.axi-jesd204-rx: AXI-JESD204-RX (1.07.a) at 0x84AA0000. Encoder 8b10b, width 4/4, lanes 4.
[ 3.669049] axi_sysid 85000000.axi-sysid-0: AXI System ID core version (1.01.a) found
[ 3.676178] axi_sysid 85000000.axi-sysid-0: [ad9695_fmc] [RX:L=4 M=2 S=1] on [zcu102] git branch <main> git <ae9605bd224fee266b226413ba3a0e0076ed3c68> dirty [2024-07-30 19:21:01] UTC
[ 3.692838] fpga_manager fpga0: Xilinx ZynqMP FPGA Manager registered
[ 4.053146] ad9208 spi1.0: ad9695 PLL LOCKED
[ 4.066852] ad9208 spi1.0: ad9695 Rev. 2 Grade 1 (API 1.0.1) probed
analog@analog:~$ iio_info ç run this
iio:device0: axi-ad9695-hpc (buffer capable)
2 channels found:
voltage0: (input, index: 0, format: le:S16/16>>0)
6 channel-specific attributes found:
attr 0: dc_filter_enable value: 0
attr 1: sampling_frequency value: 625000000
attr 2: scale value: 0.025939
attr 3: scale_available value: 0.017242 0.019073 0.025939 0.027618 0.029449 0.031127
attr 4: test_mode value: off
attr 5: test_mode_available value: off midscale_short pos_fullscale neg_fullscale checkerboard pn_long pn_short one_zero_toggle user ramp
voltage1: (input, index: 1, format: le:S16/16>>0)
6 channel-specific attributes found:
attr 0: dc_filter_enable value: 0
attr 1: sampling_frequency value: 625000000
attr 2: scale value: 0.025939
attr 3: scale_available value: 0.017242 0.019073 0.025939 0.027618 0.029449 0.031127
attr 4: test_mode value: off
attr 5: test_mode_available value: off midscale_short pos_fullscale neg_fullscale checkerboard pn_long pn_short one_zero_toggle user ramp
2 device-specific attributes found:
attr 0: sync_start_enable value: disarm
attr 1: sync_start_enable_available value: arm
2 buffer-specific attributes found:
attr 0: data_available value: 0
attr 1: length_align_bytes value: 16
No trigger on this device
iio_sysfs_trigger:
0 channels found:
2 device-specific attributes found:
attr 0: add_trigger ERROR: Permission denied (13)
attr 1: remove_trigger ERROR: Permission denied (13)
No trigger on this device
References –
Hdl
Gt_wizard readme https://wiki.analog.com/resources/fpga/docs/xgt_wizard
Petalinux users guide
Xilinx transceiver manuals
AD-SYNCHRONA14-EBZ User Guide: https://wiki.analog.com/resources/eval/user-guides/ad-synchrona14-ebz
Zcu102 board info https://www.xilinx.com/products/boards-and-kits/ek-u1-zcu102-g.html
mmc rescan mmc part fatload mmc 0:1 0x100000 BOOT.BIN fatload mmc 0:1 0x2A00000 system.dtb fatload mmc 0:1 0x3000000 Image setenv bootargs 'console=ttyPS0,115200 root=/dev/mmcblk0p2 rw earlycon rootfstype=ext4 rootwait clk_ignore_unused cpuidle.off=1' booti 0x3000000 - 0x2A00000
// SPDX-License-Identifier: GPL-2.0
/*
* Analog Devices AD9695 / AD9689 ANALOG-TO-DIGITAL CONVERTER
* https://wiki.analog.com/resources/eval/ad9208-3000ebz
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/ad9208
*
* hdl_project: <ad9695_fmc/zcu102>
* board_revision: <>
*
* Copyright (C) 2019-2022 Analog Devices Inc.
*/
#include "/home/jhardin/projects/AD9695-fmc/zcu102-A/build/tmp/work-shared/zynqmp-generic-xczu9eg/kernel-source/arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev1.0.dts"
#include </home/jhardin/projects/AD9695-fmc/zcu102-A/build/tmp/work-shared/zynqmp-generic-xczu9eg/kernel-source/include/dt-bindings/interrupt-controller/irq.h>
#include </home/jhardin/projects/AD9695-fmc/zcu102-A/build/tmp/work-shared/zynqmp-generic-xczu9eg/kernel-source/include/dt-bindings/iio/adc/adi,ad9208.h>
#include </home/jhardin/projects/AD9695-fmc/zcu102-A/build/tmp/work-shared/zynqmp-generic-xczu9eg/kernel-source/include/dt-bindings/jesd204/adxcvr.h>
&i2c1 {
i2c-mux@75 {
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
eeprom@50 {
compatible = "at24,24c02";
reg = <0x50>;
};
};
};
};
/ {
clocks {
ad9695_clkin: clock@0 {
#clock-cells = <0>;
compatible = "adjustable-clock";
clock-frequency = <625000000>;
clock-accuracy = <1000000000>;
clock-output-names = "ad9695_clk";
};
device_clk: clock@1 {
#clock-cells = <0>;
compatible = "adjustable-clock";
clock-frequency = <156250000>;
clock-accuracy = <1000000000>;
clock-output-names = "dev_clk";
};
sysref: clock@2 {
#clock-cells = <0>;
compatible = "adjustable-clock";
clock-frequency = <9765725>;
clock-accuracy = <1000000000>;
clock-output-names = "adc_sysref";
};
};
fpga_axi: fpga-axi@0 {
interrupt-parent = <&gic>;
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges = <0 0 0 0xffffffff>;
rx_dma: rx-dmac@9c400000 {
#dma-cells = <1>;
compatible = "adi,axi-dmac-1.00.a";
reg = <0x9c400000 0x1000>;
interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 71>;
adi,channels {
#size-cells = <0>;
#address-cells = <1>;
dma-channel@0 {
reg = <0>;
adi,source-bus-width = <128>;
adi,source-bus-type = <1>;
adi,destination-bus-width = <128>;
adi,destination-bus-type = <0>;
};
};
};
axi_ad9695_core: axi-ad9695-hpc@84a00000 {
compatible = "adi,axi-ad9208-1.0";
reg = <0x84a00000 0x2000>;
dmas = <&rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc0_ad9695>;
};
axi_ad9695_jesd: axi-jesd204-rx@84aa0000 {
compatible = "adi,axi-jesd204-rx-1.0";
reg = <0x84aa0000 0x4000>;
interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&zynqmp_clk 71>, <&device_clk>, <&axi_ad9695_adxcvr 0>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk";
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
adi,subclass = <0>;
#clock-cells = <0>;
clock-output-names = "jesd_adc_lane_clk";
};
axi_ad9695_adxcvr: axi-adxcvr-rx@84a60000 {
compatible = "adi,axi-adxcvr-1.0";
reg = <0x84a60000 0x10000>;
clocks = <&device_clk>, <&device_clk>;
clock-names = "conv", "div40";
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_REFCLK>;
adi,use-lpm-enable;
#clock-cells = <1>;
clock-output-names = "adc_gt_clk", "rx_out_clk";
};
axi_sysid_0: axi-sysid-0@85000000 {
compatible = "adi,axi-sysid-1.00.a";
reg = <0x85000000 0x2000>;
};
};
};
&spi0 {
status = "okay";
adc0_ad9695: ad9695@0 {
compatible = "adi,ad9695";
powerdown-gpios = <&gpio 116 0>;
fastdetect-a-gpios = <&gpio 113 0>;
fastdetect-b-gpios = <&gpio 114 0>;
spi-cpol;
spi-cpha;
spi-max-frequency = <5000000>;
reg = <0>;
clocks = <&axi_ad9695_jesd>, <&ad9695_clkin>, <&sysref>;
clock-names = "jesd_adc_clk", "adc_clk", "adc_sysref";
adi,powerdown-mode = <AD9208_PDN_MODE_POWERDOWN>;
adi,sampling-frequency = /bits/ 64 <625000000>;
adi,input-clock-divider-ratio = <1>;
adi,duty-cycle-stabilizer-enable;
adi,analog-input-neg-buffer-current = <AD9208_BUFF_CURR_600_UA>;
adi,analog-input-pos-buffer-current = <AD9208_BUFF_CURR_600_UA>;
adi,sysref-lmfc-offset = <0>;
adi,sysref-pos-window-skew = <0>;
adi,sysref-neg-window-skew = <0>;
adi,sysref-mode = <AD9208_SYSREF_CONT>;
adi,sysref-nshot-ignore-count = <0>;
/* JESD204 parameters */
adi,octets-per-frame = <1>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <2>;
adi,control-bits-per-sample = <0>;
adi,lanes-per-device = <4>;
adi,subclass = <1>;
#address-cells = <1>;
#size-cells = <0>;
};
};
========================================================================
Unique configuration/attribute values
The following attribute/value pairs are unique for one or more configuration
========================================================================
$VAR1 = 'GTHE4_QPLL0_6_25_156';
$VAR2 = {
'channel' => {},
'common' => {},
'pll_dividers' => {}
};
========================================================================
Common configuration/attribute values
The following attribute/value pairs are the same for each configuration
========================================================================
$VAR1 = 'gt_global';
$VAR2 = {
'common' => {
'QPLL1_CFG1' => '0xD038',
'POR_CFG' => '0x0',
'QPLL0_CP' => '0xFF',
'QPLL1_CFG2' => '0xFC3',
'QPLL1_CFG3' => '0x120',
'QPLL0_CFG1' => '0xD038',
'QPLL1_CP' => '0xFF',
'QPLL0_CFG3' => '0x120',
'QPLL0_CFG2' => '0xFC3',
'QPLL1_CFG4' => '0x3',
'QPLL1_CP_G3' => '0x7F',
'PPF0_CFG' => '0x800',
'QPLL0_CFG4' => '0x4',
'QPLL0_CP_G3' => '0xF',
'QPLL0_CFG1_G3' => '0xD038',
'PPF1_CFG' => '0x600',
'QPLL0_CFG2_G3' => '0xFC3',
'QPLL1_LPF' => '0x21F',
'QPLL1_CFG1_G3' => '0xD038',
'QPLL0_LPF' => '0x21F',
'QPLL1_CFG2_G3' => '0xFC3',
'QPLL0_CFG0' => '0x331C',
'QPLL1_CFG0' => '0x331C'
},
'channel' => {
'TXBUF_EN' => '"TRUE"',
'RXCDR_CFG3_GEN4' => '0x12',
'CPLL_CFG3' => '0x0',
'CPLL_CFG2' => '0x2',
'CH_HSPMUX' => '0x4444',
'CPLL_CFG1' => '0x23',
'PREIQ_FREQ_BST' => '0x1',
'RXDFE_PWR_SAVING' => '0x1',
'GEARBOX_MODE' => '0x0',
'A_TXDIFFCTRL' => '0xC',
'RXBUF_EN' => '"TRUE"',
'RXCDR_CFG3_GEN3' => '0x12',
'DEC_MCOMMA_DETECT' => '"TRUE"',
'RXPI_CFG1' => '0x0',
'RXCDR_CFG2' => '0x255',
'RXCDR_CFG3_GEN2' => '0x12',
'ALIGN_COMMA_ENABLE' => '0x3FF',
'RXCDR_CFG0' => '0x3',
'RX_WIDEMODE_CDR' => '0x0',
'ALIGN_MCOMMA_DET' => '"TRUE"',
'ALIGN_PCOMMA_DET' => '"TRUE"',
'RXCDR_CFG2_GEN4' => '0x164',
'RXGEARBOX_EN' => '"FALSE"',
'CBCC_DATA_SOURCE_SEL' => '"DECODED"',
'DEC_PCOMMA_DETECT' => '"TRUE"',
'TX_DATA_WIDTH' => '40',
'CPLL_CFG0' => '0x1FA',
'TXPH_CFG' => '0x723',
'TXGEARBOX_EN' => '"FALSE"',
'RXCDR_CFG2_GEN3' => '0x255',
'RXBUF_THRESH_UNDFLW' => '3',
'RXGBOX_FIFO_INIT_RD_ADDR' => '4',
'RXCDR_CFG3' => '0x12',
'RX_DATA_WIDTH' => '40',
'RXPI_CFG0' => '0x2004',
'RXCDR_CFG2_GEN2' => '0x255'
},
'pll_dividers' => {
'QPLL0_FBDIV' => '80',
'QPLL1_FBDIV' => '66',
'QPLL0_FBDIV_G3' => '160',
'QPLL1CLKOUT_RATE' => '"HALF"',
'TX_CLK25_DIV' => '7',
'QPLL0CLKOUT_RATE' => '"HALF"',
'RXOUT_DIV' => '2',
'QPLL1_FBDIV_G3' => '80',
'CPLL_FBDIV_45' => '5',
'CPLL_FBDIV' => '2',
'RX_CLK25_DIV' => '7',
'QPLL1_REFCLK_DIV' => '1',
'CPLL_REFCLK_DIV' => '1',
'QPLL0_REFCLK_DIV' => '1',
'TXOUT_DIV' => '2'
}
};
###############################################################################
## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
### SPDX short identifier: ADIBSD
###############################################################################
# RX parameters
set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L
set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M
set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S) ; # S
set RX_SAMPLE_WIDTH 16 ; # N/NP
set RX_SAMPLES_PER_CHANNEL [expr $RX_NUM_OF_LANES * 32 / ($RX_NUM_OF_CONVERTERS * $RX_SAMPLE_WIDTH)]
set adc_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
set adc_dma_data_width [expr $RX_SAMPLE_WIDTH * $RX_NUM_OF_CONVERTERS * $RX_SAMPLES_PER_CHANNEL]
# These are max values specific to the board
set MAX_RX_NUM_OF_LANES 4
source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
# adc peripherals
ad_ip_instance axi_adxcvr axi_ad9695_rx_xcvr [list \
NUM_OF_LANES $RX_NUM_OF_LANES \
QPLL_ENABLE 1 \
TX_OR_RX_N 0 \
SYS_CLK_SEL 3 \
OUT_CLK_SEL 3 \
]
adi_axi_jesd204_rx_create axi_ad9695_rx_jesd $RX_NUM_OF_LANES
ad_ip_parameter axi_ad9695_rx_jesd/rx CONFIG.SYSREF_IOB false
ad_ip_instance util_cpack2 util_ad9695_rx_cpack [list \
NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
]
adi_tpl_jesd204_rx_create rx_ad9695_tpl_core $RX_NUM_OF_LANES \
$RX_NUM_OF_CONVERTERS \
$RX_SAMPLES_PER_FRAME \
$RX_SAMPLE_WIDTH
ad_ip_instance clk_wiz dma_clk_wiz
ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
ad_ip_instance axi_dmac axi_ad9695_rx_dma [list \
DMA_TYPE_SRC 2 \
DMA_TYPE_DEST 0 \
CYCLIC 0 \
SYNC_TRANSFER_START 1 \
DMA_2D_TRANSFER 0 \
FIFO_SIZE 32 \
MAX_BYTES_PER_BURST 2048 \
AXI_SLICE_DEST 1 \
AXI_SLICE_SRC 1 \
DMA_LENGTH_WIDTH 24 \
DMA_DATA_WIDTH_DEST 128 \
DMA_DATA_WIDTH_SRC $adc_dma_data_width \
]
# common cores
# fPLLClkin = 325 MHz => RX_CLK25_DIV = 13
# fPLLClkout = 13000 MHz - qpll0
ad_ip_instance util_adxcvr util_ad9695_xcvr [list \
RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \
TX_NUM_OF_LANES 0 \
QPLL_FBDIV 40 \
QPLL_REFCLK_DIV 1 \
RX_OUT_DIV 1 \
RX_CLK25_DIV 13 \
POR_CFG 0x0 \
QPLL_CFG0 0x331c \
QPLL_CFG1 0xd038 \
QPLL_CFG1_G3 0xd038 \
QPLL_CFG2 0xfc3 \
QPLL_CFG2_G3 0xfc1 \
QPLL_CFG3 0x120 \
QPLL_CFG4 0x3 \
QPLL_CP 0xff \
QPLL_CP_G3 0xf \
QPLL_LPF 0x21f \
CH_HSPMUX 0x4444 \
PREIQ_FREQ_BST 1 \
RXPI_CFG0 0x104 \
RXPI_CFG1 0x0 \
RXCDR_CFG0 0x3 \
RXCDR_CFG2_GEN2 0x255 \
RXCDR_CFG2_GEN4 0x164 \
RXCDR_CFG3 0x11 \
RXCDR_CFG3_GEN2 0x12 \
RXCDR_CFG3_GEN3 0x12 \
RXCDR_CFG3_GEN4 0x12 \
]
# xcvr interfaces
set rx_ref_clk rx_ref_clk_0
create_bd_port -dir I $rx_ref_clk
create_bd_port -dir I rx_core_clk_0
ad_connect $sys_cpu_resetn util_ad9695_xcvr/up_rstn
ad_connect $sys_cpu_clk util_ad9695_xcvr/up_clk
# Rx
ad_connect ad9695_rx_device_clk rx_core_clk_0
ad_xcvrcon util_ad9695_xcvr axi_ad9695_rx_xcvr axi_ad9695_rx_jesd {} ad9695_rx_device_clk {} $MAX_RX_NUM_OF_LANES
ad_xcvrpll $rx_ref_clk util_ad9695_xcvr/qpll_ref_clk_0
for {set i 0} {$i < $MAX_RX_NUM_OF_LANES} {incr i} {
set ch [expr $i]
ad_xcvrpll $rx_ref_clk util_ad9695_xcvr/cpll_ref_clk_$ch
ad_xcvrpll axi_ad9695_rx_xcvr/up_pll_rst util_ad9695_xcvr/up_cpll_rst_$ch
}
ad_xcvrpll axi_ad9695_rx_xcvr/up_pll_rst util_ad9695_xcvr/up_qpll_rst_*
# connections (adc)
ad_connect $sys_cpu_resetn axi_ad9695_rx_dma/m_dest_axi_aresetn
ad_connect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi_aclk
ad_connect util_ad9695_rx_cpack/packed_fifo_wr axi_ad9695_rx_dma/fifo_wr
ad_connect util_ad9695_rx_cpack/packed_sync axi_ad9695_rx_dma/sync
ad_connect $sys_cpu_clk dma_clk_wiz/clk_in1
ad_connect $sys_cpu_resetn dma_clk_wiz/resetn
ad_connect ad9695_rx_device_clk rx_ad9695_tpl_core/link_clk
ad_connect ad9695_rx_device_clk util_ad9695_rx_cpack/clk
ad_connect ad9695_rx_device_clk axi_ad9695_rx_dma/fifo_wr_clk
ad_connect ad9695_rx_device_clk_rstgen/peripheral_reset util_ad9695_rx_cpack/reset
ad_connect axi_ad9695_rx_jesd/rx_sof rx_ad9695_tpl_core/link_sof
ad_connect axi_ad9695_rx_jesd/rx_data_tdata rx_ad9695_tpl_core/link_data
ad_connect axi_ad9695_rx_jesd/rx_data_tvalid rx_ad9695_tpl_core/link_valid
ad_connect rx_ad9695_tpl_core/adc_valid_0 util_ad9695_rx_cpack/fifo_wr_en
ad_connect rx_ad9695_tpl_core/adc_dovf util_ad9695_rx_cpack/fifo_wr_overflow
for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
ad_connect rx_ad9695_tpl_core/adc_enable_$i util_ad9695_rx_cpack/enable_$i
ad_connect rx_ad9695_tpl_core/adc_data_$i util_ad9695_rx_cpack/fifo_wr_data_$i
}
# interconnect (cpu)
ad_cpu_interconnect 0x44A00000 rx_ad9695_tpl_core
ad_cpu_interconnect 0x44A60000 axi_ad9695_rx_xcvr
ad_cpu_interconnect 0x44AA0000 axi_ad9695_rx_jesd
ad_cpu_interconnect 0x7c400000 axi_ad9695_rx_dma
ad_mem_hp0_interconnect $sys_cpu_clk sys_ps8/S_AXI_HP0
ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9695_rx_xcvr/m_axi
# interconnect (mem/dac)
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1
ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi
# interrupts
ad_cpu_interrupt ps-12 mb-13 axi_ad9695_rx_jesd/irq
ad_cpu_interrupt ps-13 mb-12 axi_ad9695_rx_dma/irq
