How to select dac data source by pyadi-iio or iio-oscilloscope

Hi,

That mux has a few abstraction layers over it.
Not all mux options are not exposed to the user.
The CW tones = DDS and the DAC buffer out = DMA = dac_data_in.

Andrei

Hi

    According to hdl file axi_adrv9001_tx_channel.v, line 164-176, dac_enable will be high if dac_data_sel_s set to 4'h2(dac_data_in). But actually when set  DAC buffer out at iio-oscilloscope, the dac_enable still keep low.

    So I added more signals to ila further, when set CW tones or disabled, the axi_awaddr and axi_wdata changed according with the hdl code which dac_data_sel_s turned 0(cw tones) and 3(disabled). But when setting to DAC buffer out, the axi_awaddr and axi_wdata have not any change, so I guess the mode of dac buffer out did not work normal.

when setting to disabled

when setting to cw tones:

when setting to dac buffer out:

Is there any mistake of my operations?And as mentioned earlier，how to set the mode in pyad-iio?

Thanks

Have you clicked in IIO-Osc con the "Load" button and have you received the message successfully loaded?

Take a look at the doc for sending buffers https://analogdevicesinc.github.io/pyadi-iio/buffers/index.html

Hi

    I followed your guide and set tx in pyadi-iio, but I find that only channel 1 can enable by use sdr.tx1(iq), when executing sdr.tx2(iq), the dac1_enable_i1 and dac1_enable_q1 still keep low.

   Use sdr.tx_enabled_channels and sdr.rx_enabled_channels, the results always [0], the channel 2 seems did not exits. But both channel 1 and channel 2 are enabled in profile and I actually can receive both two channels cw tones in adc1. 

Once I want to enable both channels, it returned false:

the link in  https://analogdevicesinc.github.io/pyadi-iio/buffers/index.html, some functions are not suitable to adrv9002. May I know the correct function to enable tx and rx?

Thanks

Hi,

Sorry for the delayed reply!

If you take a closer look at all the ports you will find:

dac1_*_i0
dac1_*_q0
dac1_*_i1
dac1_*_q1

dac2_*_i0
dac2_*_q0

In R1_mode (COMMON_2R2T_SUPPORT = 0, MIMO mode), dac2_*_i0 and dac2_*_q0 are not used. Also, the clock of rx1 interface drives the rx2 interface, also all data processing path up to a single DMA is driven by the same clock(adc_clock = rx/4 for LVDS)

If R1_MODE is not used dac1_*_i1 and dac1_*_q1 ports are not used. And dac1* and dac2* have separate clock domains and DMAs.

Andrei