AD9361
Recommended for New Designs
The AD9361 is a high performance, highly integrated radio
frequency (RF) Agile Transceiverâ„¢ designed for use in 3G and
4G base station applications....
AD9361 on Analog.com
Hi,
Background: I am using the Vivado HDL design given by ADI to get the hardware description and the No-OS code given by ADI to send and receive data. My eventual goal is to design 2 IPs :
Baseband Processor
Control block for AD9361
A few additional details are mentioned below:
Development Board – Zedboard
SDR – AD-FMCOMMS2-EBZ
Vivado and Vitis version – 2019.2, 2022.1, 2023.2 (Have multiple installations and have used all three for this development)
HDL project – projects/fmcomms2/zed
No-OS project - projects/ad9361
I have many queries regarding this and hope to get individual replies. I have posted 3 separate queries on the forum to make a differentiation between 3 separate themes. I have gone through the ez forum and have gotten partial answers (not enough). I have put the questions in order of priority. I am relatively new to this. Thank you in advance for your help.
HDL
Pin mapping for the SPI interface.
While using the HDL project on vivado, I was not able to locate the following pin assignments. These are ports that should somehow connect to the AD9361 board-
spi0_clk_o
spi0_sdo_o
spi0_csn_0_o
spi0_csn_1_o
spi0_csn_2_o
spi1_clk_o
spi1_sdo_o
spi1_csn_0_o
spi1_csn_1_o
spi1_csn_2_o
spi0_clk_i
spi0_sdo_i
spi0_sdi_i
spi0_csn_1
spi1_clk_i
spi0_sdo_i
spi0_sdi_i
spi0_csn_1
These ports are directly connected to the processor. Are these ports not meant to be connected to physical pins? If they are meant to be connected, how?
How to use the SPI engine IP? What is its application?
Do we need the SPI engine and its peripherals for our custom block?
I have gone through the SDR pin mapping and found that there are only 4 “SPI pins” on the FMC connector.
The document is linked here on the website under the “Design and Integration File” header. The pins are -
SPI_ENB
SPI_CLK
SPI_DO
SPI_DI
I want to introduce a BBP in the hardware description. How and where do I place this IP block in vivado?
This custom IP is supposed to act as a BBP that converts the data stream into I/Q values. I suspect that this block will be just before the “axi_ad9361” block. (That is between axi_ad9361_dac_fifo and axi_ad9361) The logic of converting data streams into I/Q values is a separate topic, and it is not in the scope of this question.
Many IP blocks that do not modify the data.
There are many IP blocks, like HDMI, audio blocks, etc., that are not used at all by the software (No-OS). Am I safe to remove these blocks? Or are these used in some internal data processing?
Can someone please explain how the "physical pins" on the zedboard be mapped to the "ports" in vivado?
I know we use the constraints file (.xdc) for this. This question arose because there are many ports that don't have any physical package pin mapping.
Why are there 2 constraint files in the vivado project?
The files are namely -
system_constr.xdc
zed_system_constr.xdc
I think “system_constr.xdc” has the AD9361 system-specific pin assignments, and the “zed_system_constr.xdc” has other assignments. Additionally, I want to ask whether the “zed_system_constr.xdc” assignments are system-critical if we wish to make simple Tx and Rx ONLY.
____________________________________
I have tried to state the problem, explain my understanding and provide any necessary links and enumeration required to better communicate the question. Kindly let me know if any additional info is required for any of the questions. I will make necessary edits to the original post, if any. Once again, I have many queries regarding this and hope to get individual replies. Thank you for your patience if reached this far in the post.
Thank You
Pranav Bhaskaran
(Student from India)
Please donot mix and match between versions. You can refer to the below link, which describes the supported vivado version, with the no-Os SW version, that you use:
https://github.com/analogdevicesinc/hdl/releases
Are you able to build FMCOMMS2 board with your BBP or ZED board successfully? If not, then would recommend you to first build it successfully using no-os drivers for better understanding.
1. No, these ports(like spi1_clk_o)are not connected to the FMC pins. Please refer to the .xdc constraint files for knowing about the FMC pin connections and the system_top.v file for the corresponding input and output ports. FYR ,Refer to the below snippet from the top.v file, that shows the port connections from the system wrapper with the "."
2. The SPI bus provides the mechanism for all digital control of the AD9361. Each SPI register is 8-bit wide, and each register
contains control bits, status monitors, or other settings that control all functions of the device.The bus is configured as a 4-wire interface by default. SPI_ENB,SPI_CLK,SPI_D0_SPI_DI are the four bus signals.
3.Yes, four pins are connected to the FMC pins. Refer to the constraint file.
6. Answered in 1.
7. For the AD-FMCOMMS2-EBZ connected to the ZED board, system_constraints.xdc file is used.
Moving to FPGA Reference designs forum for more support.
