Interfacing AD9361 with digilent zedboard using hdl/fmcomms2 and no-OS/ad9361 (1)

Please donot mix and match between versions. You can refer to the below link, which describes the supported vivado version, with the no-Os SW version, that you use:

https://github.com/analogdevicesinc/hdl/releases 

Are you able to build FMCOMMS2 board with your BBP or ZED board successfully? If not, then would recommend you to first build it successfully using no-os drivers for better understanding.

1. No, these ports(like spi1_clk_o)are not connected to the FMC pins. Please refer to the .xdc constraint files for knowing about the FMC pin connections  and the system_top.v file for the corresponding input and output ports. FYR ,Refer to the below snippet from the top.v file, that shows the port connections from the system wrapper with the "."

2. The SPI bus provides the mechanism for all digital control of the AD9361. Each SPI register is 8-bit wide, and each register
contains control bits, status monitors, or other settings that control all functions of the device.The bus is configured as a 4-wire interface by default. SPI_ENB,SPI_CLK,SPI_D0_SPI_DI are the four bus signals.

3.Yes, four pins are connected to the FMC pins. Refer to the constraint file.

6. Answered in 1.

7. For the AD-FMCOMMS2-EBZ connected to the ZED board, system_constraints.xdc file is used.

Moving to FPGA Reference designs forum for more support.

Thank you srimoyi for the detailed support.

Hi pbhereandnow ,

I just want to add a few more comments to what my colleague said, because all that was said there is right.

pbhereandnow said:

Vivado and Vitis version – 2019.2, 2022.1, 2023.2 (Have multiple installations and have used all three for this development)

Mixing them however you like, will result in inconsistencies, because Xilinx made significant updates between versions, and they work best if you choose the same Vitis and Vivado version to work together.

pbhereandnow said:

How to use the SPI engine IP? What is its application?

Do we need the SPI engine and its peripherals for our custom block?

This is the SPI Engine IP, but it is not used in this project. Are you referring to something else?

pbhereandnow said:

I want to introduce a BBP in the hardware description. How and where do I place this IP block in vivado?

https://wiki.analog.com/resources/fpga/docs/hdl/xcomm2ip

pbhereandnow said:

Am I safe to remove these blocks?

Almost. You have to check how it is used in software to know if it's safe to remove.

pbhereandnow said:

I think “system_constr.xdc” has the AD9361 system-specific pin assignments, and the “zed_system_constr.xdc” has other assignments. Additionally, I want to ask whether the “zed_system_constr.xdc” assignments are system-critical if we wish to make simple Tx and Rx ONLY.

Yes, system_constr.xdc are eval board-specific: https://analogdevicesinc.github.io/hdl/user_guide/architecture.html#project-files-for-amd-boards 

zed_system_constr.xdc are specific to Zedboard, to the carrier.

Best regards,
Iulia

Thank you for your reply,

Please note that I successfully built and flashed HDL and no-os for the FMCOMMS2 board with Zedboard. This I did without changing anything. Now, I wish to modify the existing code for my use case.

1. If ports are not connected to FMC pins, why do they exist? What is the syntax in the "system_top.v", the snippet you have attached? Is it - .{port_name} ({io_name}). Moreover this {io_name}, where and how is it used (in hw design or sw design)?
2. Is the "SPI_ENB" pin on the FMC mapped to "spi_csn" io port?
3. Noted

     6. Noted

     7. Noted. Does the .xdc have all the physical pin configurations? If yes, then I can't see the 4 SPI pin assignments here.

Thank you for your reply,

Please note that I successfully built and flashed HDL and no-os for the FMCOMMS2 board with Zedboard. This I did without changing anything. Now, I wish to modify the existing code for my use case.

iulia said:

Mixing them however you like, will result in inconsistencies,

Also, I am not mixing and matching Vivado, Vitis and No-OS versions. Instead, I have used these versions individually.

iulia said:

This is the SPI Engine IP,

Yes, in my question, I was referring to this SPI engine itself. My "custom block" should be able to send and receive spi signals, in that context, do I require this block along with it's peripherals?

iulia said:

wiki.analog.com/.../quote]

Yes, I have gone through this blog post. The files I was not able to build and get it in my system. Moreover, if you look closely towards the end of the blog, there are a few headings that don't seem to have any content. As I was to able to build this, I request you to kindly share a screengrab of the final "xcomm2ip" connected to the entire design for my reference.

iulia said:

Almost

Noted

iulia said:

zed_system_constr.xdc are specific to Zedboard, to the carrier.

Noted

[/quote]

pbhereandnow said:

do I require this block along with it's peripherals?

No.

Could you take a look at the following resources? 

https://www.mathworks.com/help/comm/ug/hdlqpsktransmitterreceiver.html

https://wiki.analog.com/resources/tools-software/linux-software/libiio/clients/qpsk_example 

iulia said:

www.mathworks.com/.../quote]

I have gone through this example. This implementation uses iio. As I am not going to use Linux (in any form) for my implementation, I cannot use this example.

iulia said:

wiki.analog.com/.../quote]

This example does not have blocks from the HDL coder library on Simulink. Hence it cannot be synthesized into an IP for vivado.

[/quote]

Hi,

This is another example on how to add an IP into our data path: https://wiki.analog.com/resources/fpga/docs/hdl/fmcomms2_fir_filt.

More than this, we cannot guide you step by step on how to implement something that wasn't either designed or provided by us.

Best regards,
Iulia