Hello
I am trying to set 4 ADCs (AD9083) to work with a single JESD quad and topology.
each AD9083 has 32 converters (16 channels of i,q) and use a single JESD lane.
The system works fine with a single lane but when scaling to 4 lanes it fails to realize it should work in multi-chip mode and I get this warning:
[ 18.381818] cf_axi_adc 84a00000.ad_ip_jesd204_tpl_adc: ADI AIM (10.03.) at 0x84A00000 mapped to 0x00000000521933dc, probed ADC AD9083 as MASTER [ 18.394794] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition initialized -> probed [ 18.406805] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition probed -> idle [ 18.418201] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition idle -> device_init [ 18.430033] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition device_init -> link_init [ 18.442298] cf_axi_adc 84a00000.ad_ip_jesd204_tpl_adc: profile0:link_num0 param L mismatch 4!=1*1 [ 18.451167] cf_axi_adc 84a00000.ad_ip_jesd204_tpl_adc: profile0:link_num0 param F mismatch 16!=64 [ 18.460040] cf_axi_adc 84a00000.ad_ip_jesd204_tpl_adc: JESD param mismatch between TPL and Link configuration ! [ 18.470132] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_init -> link_supported [ 18.482803] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_supported -> link_pre_setup [ 18.496062] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 18.509111] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 18.522250] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 18.535380] jesd204: /amba_pl@0/axi_jesd204_rx@84aa0000,jesd204:0,parent=84aa0000.axi_jesd204_rx: Possible instantiation for multiple chips; HDL lanes 4, Link[0] lanes 1 [ 18.550515] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 18.563219] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 18.576003] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 18.589313] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 18.602626] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 18.615936] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 18.638212] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 18.654275] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition clocks_enable -> link_enable [ 18.678425] ad9083 spi2.9: JESD RX (JTX) state_204b DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid [ 18.689184] ad9083 spi2.8: JESD RX (JTX) state_204b DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid [ 18.699948] ad9083 spi2.5: JESD RX (JTX) state_204b DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid [ 18.710710] ad9083 spi2.4: JESD RX (JTX) state_204b DATA, SYNC deasserted, PLL locked, PHASE established, MODE valid [ 18.721243] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_enable -> link_running [ 18.733775] jesd204: /amba_pl@0/axi_quad_spi@80010000/ad9083@4,jesd204:3,parent=spi2.4: JESD204[0:0] transition link_running -> opt_post_running_stage
the dts file I am using:
/ {
// axi_dmac@9c400000
&axi_ad9083_rx_dma {
compatible = "adi,axi-dmac-1.00.a";
#dma-cells = <1>;
#clock-cells = <0>;
};
// ad_ip_jesd204_tpl_adc@84a00000
&rx_ad9083_tpl_core_adc_tpl_core {
compatible = "adi,axi-ad9083-rx-1.0";
dmas = <&axi_ad9083_rx_dma 0>;
dma-names = "rx";
spibus-connected = <&adc3_ad9083>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9083_rx_jesd_rx_axi 0 0>;
};
// axi_jesd204_rx@84aa0000
&axi_ad9083_rx_jesd_rx_axi {
compatible = "adi,axi-jesd204-rx-1.0";
clocks = <&zynqmp_clk 71>, <&ad9528 0>, <&axi_ad9083_rx_xcvr 0>, <&rx_fixed_link_clk>;
clock-names = "s_axi_aclk", "device_clk", "lane_clk", "link_clk";
#clock-cells = <0>;
clock-output-names = "jesd_rx_lane_clk";
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&axi_ad9083_rx_xcvr 0 0>;
};
// axi_adxcvr@84a60000
&axi_ad9083_rx_xcvr {
compatible = "adi,axi-adxcvr-1.0";
clocks = <&zynqmp_clk 71>, <&ad9528 4>;
clock-names = "s_axi_aclk", "conv";
#clock-cells = <1>;
clock-output-names = "rx_gt_clk", "rx_out_clk";
adi,sys-clk-select = <3>; // XCVR_QPLL
adi,out-clk-select = <4>; // XCVR_REFCLK_DIV2
adi,use-lpm-enable;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&ad9528 0 0>;
};
// axi_sysid@85000000
&axi_sysid_0 {
compatible = "adi,axi-sysid-1.00.a";
};
&axi_quad_spi_0 {
status = "okay";
//spidev@2{
// compatible = "rohm,dh2228fv";
// reg = <2>;
// spi-max-frequency = <1000000>;
// status = "okay";
//};
adc0_ad9083: ad9083@4 {
compatible = "adi,ad9083";
reg = <4>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>;
jesd204-link-ids = <0>;
jesd204-inputs = <&adc1_ad9083 0 0>;
/* JESD204 parameters */
adi,octets-per-frame = <64>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <32>;
adi,control-bits-per-sample = <0>;
adi,lanes-per-device = <1>;
adi,subclass = <0>;
/* software reset, resistor is not mounted */
/* reset-gpios = <&gpio 111 0>; */
pwdn-gpios = <&gpio 110 0>;
};
adc1_ad9083: ad9083@5 {
compatible = "adi,ad9083";
reg = <5>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&adc2_ad9083 0 0>;
/* JESD204 parameters */
adi,octets-per-frame = <64>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <32>;
adi,control-bits-per-sample = <0>;
adi,lanes-per-device = <1>;
adi,subclass = <0>;
/* software reset, resistor is not mounted */
/* reset-gpios = <&gpio 111 0>; */
pwdn-gpios = <&gpio 110 0>;
};
adc2_ad9083: ad9083@8 {
compatible = "adi,ad9083";
reg = <8>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&adc3_ad9083 0 0>;
/* JESD204 parameters */
adi,octets-per-frame = <64>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <32>;
adi,control-bits-per-sample = <0>;
adi,lanes-per-device = <1>;
adi,subclass = <0>;
/* software reset, resistor is not mounted */
/* reset-gpios = <&gpio 111 0>; */
pwdn-gpios = <&gpio 110 0>;
};
adc3_ad9083: ad9083@9 {
compatible = "adi,ad9083";
reg = <9>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-inputs = <&rx_ad9083_tpl_core_adc_tpl_core 0 0>;
/* JESD204 parameters */
adi,octets-per-frame = <64>;
adi,frames-per-multiframe = <32>;
adi,converter-resolution = <16>;
adi,bits-per-sample = <16>;
adi,converters-per-device = <32>;
adi,control-bits-per-sample = <0>;
adi,lanes-per-device = <1>;
adi,subclass = <0>;
/* software reset, resistor is not mounted */
/* reset-gpios = <&gpio 111 0>; */
pwdn-gpios = <&gpio 110 0>;
};
};
The parameter sets for FPGA:
It is possible that the tpl core is limited in number of converters it can handle, but the but width is was I am expecting to get.
Will appreciate any advice
Thanks
Edited title for clarity
[edited by: iulia at 9:52 AM (GMT -4) on 19 Jul 2024]
