How to control TDD in a custom adrv9002 FPGA design

Question

Hi 
 I'm using iio-oscillscope and linux/hdl built from source to debug adrv9002. I want to transmit and receive data from/to my custom HDL design rather than from/to arm, so I need to control my data stream and RF enable/disable by myself. I found in axi_adrv9001.v: 
 rx1_enbale = tdd_if1_mode ? tdd_rx1_rf_en:gpio_rx1_enable_in; 
 .... 
 Is that mean signal tdd_rx1_rf_en is from Automated TDD in profile file and gpio_rx1_enable_in is from user defined pin, if I need receive data, only need set tdd_if1_mode to 0 and gpio_rx1_enable_in set to 1, and no more rf control signal needed? 
 Other question is there only tx1_enable/tx2_enable/rx1_enable/rx2_enable, how to enable observation channel, exist other pins or it is default enable when tx enable. 
 
 Thanks

andrei_g · Accepted Answer

Hi, 
 Take a look at the generic axi tdd doc and the Regmap of the tdd integrated in the axi_adrv9001 analogdevicesinc.github.io/.../index.html https://wiki.analog.com/resources/eval/user-guides/adrv9002/axi_adrv9002#register_map 
 mozhoudonglu said: Other question is there only tx1_enable/tx2_enable/rx1_enable/rx2_enable, how to enable observation channel, exist other pins or it is default enable when tx enable. 
 Section "Observation Receiver (ORx) Enable Control" page 236 from adrv9001 user guide. "The ADRV9001 Receiver can be reused as an observation channel through either port A or B.Assign a DGPIO pin as an ORx enable signal once the ORx channel is configured. The BBIC can toggle the DGPIO in the transmitter RF-enabled state to enable/disable the ORx channel. Note that ORx enable timing should only be the subset of the transmitter enable timing. The enum ADI_ADRV9001_GPIO_SIGNAL_ORX_ENABLE_1/ ADI_ADRV9001_GPIO_SIGNAL_ORX_ENABLE_2 is defined for DPGIO as the ORx enable signal. Set the DPGIO assignment by the API adi_adrv9001_gpio_Configure()." 
 https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/adi-adrv9002.dtsi#L64-L77 
 Andrei)

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How to control TDD in a custom adrv9002 FPGA design

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