adrv9002+zcu102 fpga hdl

Hi, yes you can modify the HDL designs.

the system_top.v wraps the block diagram generated by the system_bd.tcl

The project wiki page is at https://wiki.analog.com/resources/eval/user-guides/adrv9001 and ref design at https://wiki.analog.com/resources/eval/user-guides/adrv9002/reference_hdl .

The main IP (AXI ADRV9002) doc is available at https://wiki.analog.com/resources/eval/user-guides/adrv9002/axi_adrv9002 and source code at https://github.com/analogdevicesinc/hdl/tree/main/library/axi_adrv9001 .

There is also a testbench to help you test your changes in a simulation at https://github.com/analogdevicesinc/testbenches/tree/main/adrv9001 .

A comprehensive user guide for the HDL repository is available at http://analogdevicesinc.github.io/hdl/user_guide/index.html , as well all documentation for our open-source HDL IPs.

Regards,

Hi

    Thank you very much and I will follow the guide to design. By the way, is there any command or sctrpts that can show source .v file rather than ip which was packaged

     The makefile under /projects/adrv9001/zcu102 shows it depends library axi_adrv9001、axi_dmac、axi_sysid、sysid_rom、util_cpack2、util_upack2，I followed link https://analogdevicesinc.github.io/hdl/user_guide/ip_cores/use_adi_ips.html and use command make -C library all to build all library, the 6 libraries above build success. But comapred to the hierarchy of project adrv9001(as picture shows), some modules miss. There modules are axi_cpu_interconnect,spi0_csn_concat,spi1_csn_concat,sys_*_rstgen,sys_concat_intc_* and the zynqMP process sys_ps8. I searched the all file system and did not find corresponding verilog source code.

Thanks

Those are Xilinx-specific IPs, and I'm not sure if they have the source code published for that as I have never searched for them, but you can check online.