axi_ad9361 IP testing

Question

Hi, 
 I would like to know how can I test axi_ad9361 IP alone without Fmcomms OR AD9361 Hardware board. I came across ad9361_bist_loopback, and would appreciate help in the below. 
 1. Is FIFO required for this test? 
 2. Could I use this for testing the IP alone. 
 If so will I require IIO oscilloscope along with libiio text files for I,Q data (from github). 
 3. Can I test axi_ad9361 IP with ILA. Can I have AD9361 functionalities in the IP without decimator interpolator IP? 
 
 Thanks in advance 
 Jyothi

JMarques · Accepted Answer

Yes, the folder structure is correct. The testbenches uses the IPs from the HDL repo and are automatically built when you do "make" in a testbench project. The Vivado flow copies the IPs source into the created testbench project, that means, vivado will "copy" the IP sources to these paths: hdl/testbenches//runs/cfg*/cfg*.ip_user_files/bd/test_harness/ipshared/* hdl/testbenches//runs/cfg*/cfg*.gen/sources_1/bd/test_harness/ipshared/* After the tb project is created, editing the hdl/library/ sources won't automatically update the test program in execution, you have to either do "make" again (preferred) or patch the folders mentioned above (experienced). The only exception are the test_program.sv files. The testbench project may or may not use a hdl/projects/ source code; it really depends on the requirements and on what is being tested.)

JMarques · Answer

See https://wiki.analog.com/resources/fpga/docs/axi_ad9361 
 pretty much connect clk_out to clk_in, frame_out to frame_in, and data_out to data_in to create a loopback

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