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axi_ad9361 IP testing

Category: Software
Product Number: AD9361
Software Version: VIvado 2021.2

Hi,

I would like to know how can I test axi_ad9361 IP alone without Fmcomms OR AD9361 Hardware board. I came across ad9361_bist_loopback, and would appreciate help in the below.

1. Is FIFO required for this test?

2. Could I use this for testing the IP alone.

     If so will I  require IIO oscilloscope along with libiio text files for I,Q data (from github). 

3. Can I test axi_ad9361 IP with ILA. Can I have AD9361 functionalities in the IP without decimator interpolator IP?

Thanks in advance

Jyothi

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  • Hi, the mainland testbench repo is

    https://github.com/analogdevicesinc/testbenches/

    and need to be cloned inside the HDL repo as described in the Readme. Let me know if you followed these steps and attach any relevant log file.

    Just tested the tb with Vivado 2023.2. `make MODE=gui` allows to run the tb in gui mode.

  • Hi,

    Thanks for your help, I have cloned the testbenches as per the steps but everytime I run "make MODE=gui" I am not seeing required waveforms on the simulation window. All waveforms are having value 0 though adc i0,q0,q1,i1 seem to go high for a spcific interval of time but again drops to 0.

    I am not able to attach any images though.

    I am having two simulation windows and the one required named cfg1.wcfg has all  waveforms with value '0', while the untitled simulation window I am not sure if required, has garbage waveforms.

    The test log file has vivado version and start gui command. 

    Also, when the vivado GUI opens, it states the file has only "read only" option, open directory instead. When I click Ok, I get the simulation window but with the waveforms as stated above. 

    Would greatly appreciate support.

    Thanks and regards,

  • You can add any signal to the waveform window, the simulation just needs to be paused.

    The "read only" popup does not matter.

    The simulation main code is in the test_program.sv file.

    There are many resources online on getting familiar with Vivado tools.

  • Hi,

    Thank you for the support from your side, I am having an idea of what has to be done, although I would really appreciate if you could help me understand a little more. 

    As per my understanding the testbenches have its own project source and does not require any project as reference for carrying out simulation.  I need to give waveforms during simulation or in testbench soucre test_program.sv.

    Is my understanding correct? If so, the steps for cloning clearly states folder structure to be :

    • library
    • projects
    • testbenches

    I have followed the same for cloning the testbenches but it doesnt actually matter cause the testbench is having its own source ?

    I  would really appreciate to get to know about this test code, but I have not been able to find any source for it. Any link or data about this testcode would be of great help.

    Thanks & Regards

                             

  • Yes, the folder structure is correct.

    The testbenches uses the IPs from the HDL repo and are automatically built when you do "make" in a testbench project.

    The Vivado flow copies the IPs source into the created testbench project, that means, vivado will "copy" the IP sources to these paths:

    hdl/testbenches/<TESTBENCH>/runs/cfg*/cfg*.ip_user_files/bd/test_harness/ipshared/*

    hdl/testbenches/<TESTBENCH>/runs/cfg*/cfg*.gen/sources_1/bd/test_harness/ipshared/*

    After the tb project is created, editing the hdl/library/<IP_CORE> sources won't automatically update the test program in execution, you have to either do "make" again (preferred) or patch the folders mentioned above (experienced). The only exception are the test_program.sv files.

    The testbench project may or may not use a hdl/projects/<PROJECT> source code; it really depends on the requirements and on what is being tested.