axi_ad9361 IP testing

FPGAdesigner said:

I came across ad9361_bist_loopback, and would appreciate help in the below.

You cannot test BIST without actual AD9361 hardware , as BIST generator is internal to the  AD9361 chip. Refer to the below block diagram. The AXI_AD9361 IP core interfaces to the AD9361 chip

Refer to the below wiki page for more details:

https://wiki.analog.com/resources/fpga/docs/axi_ad9361 

Hi,

 Thanks for the quick response, I have gone through the link mentioned by you multiple times. I want to know how could I test the IP alone?

Testing of IP alone will be phase1 of my project and after searching multiple threads I came across FMCOMMS2 testbench and ILA usage for DAC and ADC.

Though I could not find how exactly could I work with them without hardware board. I have my FPGA board with me, But FMCOMMS2 board is the next phase of my project.

Could you please help, and guide a way to test the IP ?

Thanks & Regards. 

Moving to FPGA reference designs forum

See https://wiki.analog.com/resources/fpga/docs/axi_ad9361

pretty much connect clk_out to clk_in, frame_out to frame_in, and data_out to data_in to create a loopback

Hi,

Thank you for the idea, but my concern is if I simply give a connection from outputs to inputs to create loopback, I will not be having inputs/outputs since no analog data is provided on input side.

If I consider DDS IP from AMD  as input analog source and then create this loopback, will that work?

Please note this is my first time working with ADCs and DACs and I am kind of struggling, Would appreciate any ideas/suggestions from your side. 

Thanks & Regards

Hi,

Thank you for the idea, but my concern is if I simply give a connection from outputs to inputs to create loopback, I will not be having inputs/outputs since no analog data is provided on input side.

If I consider DDS IP from AMD  as input analog source and then create this loopback, will that work?

Please note this is my first time working with ADCs and DACs and I am kind of struggling, Would appreciate any ideas/suggestions from your side. 

Thanks & Regards

After creating the internal loopback in the FPGA, use the driver (no-OS (main.c), Linux) to provide data to the DAC interface.

I'm unable to provide in-depth support for designs using the IP standalone, without using the reference design provided.

Hi, 

Thanks for the quick response, I think I am able to follow you. But if you can provide more clarity I would really appreciate it. 

I am using fmcomms2+zed board reference design 

https://github.com/analogdevicesinc/hdl/tree/main/projects/fmcomms2/zed

as provided by above link.

I have tried to attach the testbench too as provided on

https://github.com/ronagyl/testbenches/tree/main/fmcomms2 but was not able to do so, for some unknown reasons. 

Would really appreciate support from you.

Thanks & Regards

Hi, the mainland testbench repo is

https://github.com/analogdevicesinc/testbenches/

and need to be cloned inside the HDL repo as described in the Readme. Let me know if you followed these steps and attach any relevant log file.

Just tested the tb with Vivado 2023.2. `make MODE=gui` allows to run the tb in gui mode.

Hi,

Thanks for your help, I have cloned the testbenches as per the steps but everytime I run "make MODE=gui" I am not seeing required waveforms on the simulation window. All waveforms are having value 0 though adc i0,q0,q1,i1 seem to go high for a spcific interval of time but again drops to 0.

I am not able to attach any images though.

I am having two simulation windows and the one required named cfg1.wcfg has all  waveforms with value '0', while the untitled simulation window I am not sure if required, has garbage waveforms.

The test log file has vivado version and start gui command. 

Also, when the vivado GUI opens, it states the file has only "read only" option, open directory instead. When I click Ok, I get the simulation window but with the waveforms as stated above. 

Would greatly appreciate support.

Thanks and regards,

You can add any signal to the waveform window, the simulation just needs to be paused.

The "read only" popup does not matter.

The simulation main code is in the test_program.sv file.

There are many resources online on getting familiar with Vivado tools.

Hi,

Thank you for the support from your side, I am having an idea of what has to be done, although I would really appreciate if you could help me understand a little more. 

As per my understanding the testbenches have its own project source and does not require any project as reference for carrying out simulation.  I need to give waveforms during simulation or in testbench soucre test_program.sv.

Is my understanding correct? If so, the steps for cloning clearly states folder structure to be :

• library
• projects
• testbenches

I have followed the same for cloning the testbenches but it doesnt actually matter cause the testbench is having its own source ?

I  would really appreciate to get to know about this test code, but I have not been able to find any source for it. Any link or data about this testcode would be of great help.

Thanks & Regards

Yes, the folder structure is correct.

The testbenches uses the IPs from the HDL repo and are automatically built when you do "make" in a testbench project.

The Vivado flow copies the IPs source into the created testbench project, that means, vivado will "copy" the IP sources to these paths:

hdl/testbenches/<TESTBENCH>/runs/cfg*/cfg*.ip_user_files/bd/test_harness/ipshared/*

hdl/testbenches/<TESTBENCH>/runs/cfg*/cfg*.gen/sources_1/bd/test_harness/ipshared/*

After the tb project is created, editing the hdl/library/<IP_CORE> sources won't automatically update the test program in execution, you have to either do "make" again (preferred) or patch the folders mentioned above (experienced). The only exception are the test_program.sv files.

The testbench project may or may not use a hdl/projects/<PROJECT> source code; it really depends on the requirements and on what is being tested.