Category: Hardware
Product Number: AD9081
Hi everyone,
we have a setup with a ZCU102 board and an AD9081-EBZ board.
We are trying a configuration with DAC clock at 12 GHz and ADC clock at 3 GHz. Interpolation is 8x1 and decimation is 4x8. From mxFE JESD204x Mode Selector tool we found that suitable JESD204B modes are Mode 62 for tx and mode 3.00 for rx:
Tx Mode: JESD Mode Number 62 txBW 1200.0 Total Int 8 Coarse Int 8 Fine Int 1 Dual Link False JESD Deframer JESD204B L 4 M 2 F 1 S 1 K 32 N 16 NP 16 LaneRate 15.0 Rx Mode: JESD Mode Number 3.00 rxBW 76.31 Total Dec 32 Coarse Dec 4 Fine Dec 8 Dual Link False JESD Framer JESD204B Async False L 1 M 2 F 4 S 1 K 32 NP 16 LaneRate 3.75
Using pyadi-jif and pyadi-dt we obtained the make command to generate HDL and the devicetree:
make JESD_MODE=8B10B RX_LANE_RATE=3 RX_JESD_L=1 RX_JESD_M=2 RX_JESD_S=1 TX_LANE_RATE=15 TX_JESD_L=4 TX_JESD_M=2 TX_JESD_S=1
// SPDX-License-Identifier: GPL-2.0
// AUTOGENERATED BY PYADI-DT <date>
/*
* Analog Devices AD9081-FMC-EBZ
* https://wiki.analog.com/resources/eval/user-guides/quadmxfe/quick-start
* https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081
*
* hdl_project: <ad9081_fmca_ebz/zcu102>
* board_revision: <>
*
* Copyright (C) 2021 Analog Devices Inc.
*/
#include "zynqmp-zcu102-rev10-ad9081.dts"
#define CDDC_I 0
#define CDDC_Q 1
&axi_ad9081_rx_jesd {
clocks = <&zynqmp_clk 71>, <&hmc7044 10>, <&axi_ad9081_adxcvr_rx 1>, <&axi_ad9081_adxcvr_rx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
};
&axi_ad9081_tx_jesd {
clocks = <&zynqmp_clk 71>, <&hmc7044 6>, <&axi_ad9081_adxcvr_tx 1>, <&axi_ad9081_adxcvr_tx 0>;
clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk";
};
&axi_ad9081_adxcvr_rx {
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_PROGDIV_CLK>;
};
&axi_ad9081_adxcvr_tx {
adi,sys-clk-select = <XCVR_QPLL>;
adi,out-clk-select = <XCVR_PROGDIV_CLK>;
};
// &axi_ad9081_adxcvr_tx: axi-adxcvr-tx {
// adi,sys-clk-select = <XCVR_QPLL>;
// adi,out-clk-select = <XCVR_REFCLK_DIV2>;
// };
// &axi_ad9081_adxcvr_tx: axi-adxcvr-tx@84b60000 {
// adi,sys-clk-select = <XCVR_QPLL>;
// adi,out-clk-select = <XCVR_PROGDIV_CLK>;
// };
&spi1 {
status = "okay";
hmc7044: hmc7044@0 {
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
compatible = "adi,hmc7044";
reg = <0>;
spi-max-frequency = <1000000>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-sysref-provider;
adi,jesd204-max-sysref-frequency-hz = <2000000>; /* 2 MHz */
/*
* There are different versions of the AD9081-FMCA-EBZ & AD9082-FMCA-EBZ
* VCXO = 122.880 MHz, XO = 122.880MHz (AD9081-FMC-EBZ & AD9082-FMC-EBZ)
* VCXO = 100.000 MHz, XO = 100.000MHz (AD9081-FMC-EBZ-A2 & AD9082-FMC-EBZ-A2)
* To determine which board is which, read the freqency printed on the VCXO
* or use the fru-dump utility:
* #fru-dump -b /sys/bus/i2c/devices/15-0050/eeprom
*/
//adi,pll1-clkin-frequencies = <122880000 30720000 0 0>;
//adi,vcxo-frequency = <122880000>;
adi,pll1-clkin-frequencies = <100000000 10000000 0 0>;
adi,vcxo-frequency = <100000000>;
adi,pll1-loop-bandwidth-hz = <200>;
adi,pll2-output-frequency = <3000000000>;
adi,sysref-timer-divider = <1024>;
adi,pulse-generator-mode = <0>;
adi,clkin0-buffer-mode = <0x07>;
adi,clkin1-buffer-mode = <0x07>;
adi,oscin-buffer-mode = <0x15>;
adi,gpi-controls = <0x00 0x00 0x00 0x00>;
adi,gpo-controls = <0x37 0x33 0x00 0x00>;
clock-output-names =
"hmc7044_out0", "hmc7044_out1", "hmc7044_out2",
"hmc7044_out3", "hmc7044_out4", "hmc7044_out5",
"hmc7044_out6", "hmc7044_out7", "hmc7044_out8",
"hmc7044_out9", "hmc7044_out10", "hmc7044_out11",
"hmc7044_out12", "hmc7044_out13";
hmc7044_c02:channel@2 {
reg = <2>;
adi,extended-name = "DEV_REFCLK";
adi,divider = <16>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c03:channel@3 {
reg = <3>;
adi,extended-name = "DEV_SYSREF";
adi,divider = <2048>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c013:channel@13 {
reg = <13>;
adi,extended-name = "FPGA_SYSREF";
adi,divider = <2048>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c00:channel@0 {
reg = <0>;
adi,extended-name = "CORE_CLK_RX";
adi,divider = <32>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c010:channel@10 {
reg = <10>;
adi,extended-name = "CORE_CLK_RX_ALT";
adi,divider = <32>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c08:channel@8 {
reg = <8>;
adi,extended-name = "FPGA_REFCLK1";
adi,divider = <32>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c06:channel@6 {
reg = <6>;
adi,extended-name = "CORE_CLK_TX";
adi,divider = <8>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
hmc7044_c012:channel@12 {
reg = <12>;
adi,extended-name = "FPGA_REFCLK2";
adi,divider = <32>;
adi,driver-mode = <HMC7044_DRIVER_MODE_LVDS>;
};
};
};
&fmc_spi {
trx0_ad9081: ad9081@0 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "adi,ad9081";
reg = <0>;
spi-max-frequency = <5000000>;
/* Clocks */
clocks = <&hmc7044 2>;
clock-names = "dev_clk";
clock-output-names = "rx_sampl_clk", "tx_sampl_clk";
#clock-cells = <1>;
jesd204-device;
#jesd204-cells = <2>;
jesd204-top-device = <0>; /* This is the TOP device */
jesd204-link-ids = <FRAMER_LINK0_RX DEFRAMER_LINK0_TX>;
jesd204-ignore-errors;//DEBUG ONLY REMOVE LATER!!
jesd204-inputs =
<&axi_ad9081_core_rx 0 FRAMER_LINK0_RX>,
<&axi_ad9081_core_tx 0 DEFRAMER_LINK0_TX>;
adi,tx-dacs {
#size-cells = <0>;
#address-cells = <1>;
adi,dac-frequency-hz = /bits/ 64 <12000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <8>;
ad9081_dac0: dac@0 {
reg = <0>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_dac1: dac@1 {
reg = <1>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_dac2: dac@2 {
reg = <2>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
ad9081_dac3: dac@3 {
reg = <3>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
adi,interpolation = <1>;
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_tx_jesd_l0: link@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
adi,logical-lane-mapping = /bits/ 8 <0 2 7 7 1 7 7 3>;
adi,link-mode = <62>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <2>; /* JESD M */
adi,octets-per-frame = <1>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <4>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
adi,tpl-phase-adjust = <13>;
};
};
};
adi,rx-adcs {
#size-cells = <0>;
#address-cells = <1>;
adi,adc-frequency-hz = /bits/ 64 <3000000000>;
adi,main-data-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_adc0:adc@0 {
reg = <0>;
adi,decimation = <4>;
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
adi,nco-mixer-mode = <AD9081_ADC_NCO_VIF>;
//adi,crossbar-select = <&ad9081_rx_fddc_chan0>, <&ad9081_rx_fddc_chan2>; /* Static for now */
};
};
adi,channelizer-paths {
#address-cells = <1>;
#size-cells = <0>;
ad9081_rx_fddc_chan0:channel@0 {
reg = <0>;
adi,decimation = <8>;
adi,gain = <2048>; /* 2048 * 10^(gain_dB/20) */
adi,nco-frequency-shift-hz = /bits/ 64 <0>;
};
};
adi,jesd-links {
#size-cells = <0>;
#address-cells = <1>;
ad9081_rx_jesd_l0: link@0 {
reg = <0>;
adi,converter-select =
<&ad9081_rx_fddc_chan0 FDDC_I>, <&ad9081_rx_fddc_chan0 FDDC_Q>;
adi,logical-lane-mapping = /bits/ 8 <2 0 7 7 7 7 3 1>;
adi,link-mode = <3>; /* JESD Quick Configuration Mode */
adi,subclass = <1>; /* JESD SUBCLASS 0,1,2 */
adi,version = <1>; /* JESD VERSION 0=204A,1=204B,2=204C */
adi,dual-link = <0>; /* JESD Dual Link Mode */
adi,converters-per-device = <2>; /* JESD M */
adi,octets-per-frame = <4>; /* JESD F */
adi,frames-per-multiframe = <32>; /* JESD K */
adi,converter-resolution = <16>; /* JESD N */
adi,bits-per-sample = <16>; /* JESD NP' */
adi,control-bits-per-sample = <0>; /* JESD CS */
adi,lanes-per-device = <1>; /* JESD L */
adi,samples-per-converter-per-frame = <1>; /* JESD S */
adi,high-density = <0>; /* JESD HD */
};
};
};
};
};
&axi_ad9081_core_tx {
single-shot-output-gpios = <&gpio 139 0>;
};When we try to boot with the generated HDL and devicetree we see that the JESD TX link goes up correctly and is in DATA mode, while the JESD RX link shows some problems and is in CGS mode and the "Measured Link Clock" has a wrong value. This is a screenshot from jesd_status:
If we remove the line "jesd204-ignore-errors;" the FSM fails and the link is disabled. Below is the dmesg output of the system, showing errors about setting the SYSREF ("hmc7044_jesd204_link_pre_setup: Link2 setting SYSREF rate 2929687 failed (-22)") and QPLL error ("adxcvr_clk_enable: QPLL RX buffer underflow error, status: 0x61").
[ 6.758776] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition initialized -> probed [ 6.769475] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition initialized -> probed [ 6.780172] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition probed -> idle [ 6.790252] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition probed -> idle [ 6.800344] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition idle -> device_init [ 6.810858] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition idle -> device_init [ 6.821384] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition device_init -> link_init [ 6.832332] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition device_init -> link_init [ 6.843297] jesd204: /axi/spi@ff050000/hmc7044@0,jesd204:1,parent=spi2.0: JESD204[0:0] In link_supported got error from cb: -22 (ignoring!) [ 6.855821] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_init -> link_supported [ 6.867040] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_init -> link_supported [ 6.878252] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link2 setting SYSREF rate 2929687 failed (-22) [ 6.887899] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link2 setting SYSREF rate 2929687 failed (-22) [ 6.897712] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link2 forcing continuous SYSREF mode [ 6.906572] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link0 setting SYSREF rate 2929687 failed (-22) [ 6.916224] hmc7044 spi2.0: hmc7044_jesd204_link_pre_setup: Link0 setting SYSREF rate 2929687 failed (-22) [ 6.926074] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_supported -> link_pre_setup [ 6.937722] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_supported -> link_pre_setup [ 6.961722] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_pre_setup -> clk_sync_stage1 [ 6.973455] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_pre_setup -> clk_sync_stage1 [ 6.985191] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage1 -> clk_sync_stage2 [ 6.997013] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage1 -> clk_sync_stage2 [ 7.008839] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage2 -> clk_sync_stage3 [ 7.020664] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage2 -> clk_sync_stage3 [ 7.034527] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clk_sync_stage3 -> link_setup [ 7.045913] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clk_sync_stage3 -> link_setup [ 7.062314] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_setup -> opt_setup_stage1 [ 7.073786] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_setup -> opt_setup_stage1 [ 7.090354] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage1 -> opt_setup_stage2 [ 7.102353] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage1 -> opt_setup_stage2 [ 7.114638] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage2 -> opt_setup_stage3 [ 7.126633] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage2 -> opt_setup_stage3 [ 7.138629] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage3 -> opt_setup_stage4 [ 7.150619] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage3 -> opt_setup_stage4 [ 7.162624] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage4 -> opt_setup_stage5 [ 7.174621] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage4 -> opt_setup_stage5 [ 7.221992] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL RX buffer underflow error, status: 0x61 [ 7.231976] axi_adxcvr 84a60000.axi-adxcvr-rx: adxcvr_clk_enable: QPLL RX buffer overflow error, status: 0x61 [ 7.246051] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition opt_setup_stage5 -> clocks_enable [ 7.257787] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition opt_setup_stage5 -> clocks_enable [ 7.269578] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition clocks_enable -> link_enable [ 7.280882] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition clocks_enable -> link_enable [ 7.544305] axi-jesd204-rx 84a90000.axi-jesd204-rx: axi_jesd204_rx_jesd204_link_running: Link2 status failed (CGS) [ 7.554653] jesd204: /fpga-axi@0/axi-jesd204-rx@84a90000,jesd204:4,parent=84a90000.axi-jesd204-rx: JESD204[0:2] In link_running got error from cb: -1 (ignoring!) [ 7.664538] ad9081 spi1.0: JESD RX (JTX) Link2 in CGS, SYNC asserted, PLL locked, PHASE established, MODE valid [ 7.674630] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] In link_running got error from cb: -1 (ignoring!) [ 7.687057] ad9081 spi1.0: JESD TX (JRX) Link0 0xF lanes in DATA [ 7.693112] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_enable -> link_running [ 7.704328] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_enable -> link_running [ 7.715545] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:2] transition link_running -> opt_post_running_stage [ 7.727710] jesd204: /axi/spi@ff040000/ad9081@0,jesd204:0,parent=spi1.0: JESD204[0:0] transition link_running -> opt_post_running_stage
Thank you in advance!
Fabio
