I would like to loop back my rx signal to the tx output of the ad9361, but I would like to implement this in the fpga, so I don't need to set this setting every time on start up. which connection should I make on my axi_ad9361?
Hi, loopback the following signals: *_data_*, *_clk_*, and *_frame_*. E.g., for CMOS, loopback the signals highlighted:
For LVDS, the signals are the same but differential pairs (e.g. rx_frame_in_n/p, as shown in the interface ports table)
See http://analogdevicesinc.github.io/hdl/library/axi_ad9361/index.html for a preview of the IP block.
You can edit the bd tcl to create the loopback instead of the ports. Just also make sure to remove the removed ports from the xdc (cmos, lvds)
Regards,
