Continuous Data

Moving to FPGA reference designs forum.

Hi faruqi ,

Is this a reference design that we provided?

Best regards,
Iulia

Yes I am working on FMCOMMS3 Board and its reference design for Linux.

The data being transferred to PS using ADC DMA is not continuous. it is being dropped. I want to know how to find out about buffer length so the data is not dropped. I also have to perform FFT processing on the data samples. This takes certain time. so how to do processing and continuously read data from buffers without losing samples. the main issue I am facing is not about data loss rather the next read cycle begins from arbitrary location. I need to read data from certain location every time. one option is to read data continuously. other option is to generate trigger but hoe to do it in HDL??

Hi,

Could you take a look at this thread?  Continuously Stream Rx data to PS using ADI AXI DMA  

Best regards,
Iulia

I am still unable to understand objectively that what should be the buffer length, if an 'x' time is used for processing??

Is there any formula, the link you posted only tells me that what can be the maximum buffer length? is there any way I can find it myself?

There is no formula on how much time the processing system will take to process the data. What you can do is to create a C/C++ leveraging libIIO to iterate buffers configurations

Can we not do it in PyADI IIO???

Yes you can, just be aware that python is interpreted and performance may be worse due to the evaluation.

Do you have any example in C which runs on Linux?

github.com/.../examples