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AD9695_fmc/ZCU102 modify the util_ad9695_xcvr for the the -625 speed grade

Category: Software
Product Number: AD9695
Software Version: vivado 2023.2

how do I modify the util_ad9695_xcvr for the -625 speed grade?

it looks like the only thing that needs to be changed is the lane rate. 

The documentation alludes to things need to be changed, but only says to use the wizard. the wizards values dont line up by the same names. the parser perl script wont pull values from the IP since it was not made with the wizard.

https://wiki.analog.com/resources/fpga/docs/util_xcvr

Im also not sure if any other IP blocks in the reference design need to be changed.

  • Hi,

    Just to confirm, did you use the Xilinx Transceiver Wizard?

    Did you check out this Xilinx Product Selection Guide? (if it's UltraScale+ that you want)

    What FPGA are you intending to use? And what about the JESD configuration?

    Best regards,
    Iulia

  • I didn't use the wizard because the IP block was integrated from the ADI example (\hdl\library\xilinx\util_adxcvr) rather than being generated by a wizard.

    I use the JESD settings from the example project provided, but reduce clock speeds, based on ratios, for the lower speed grade. I may further modify it for subclass 0, to eliminate the need for sysref, given Im only using one AD9695. The sysref is not as clear to derive at this point.

    Hardware Details:

    • Platform: ZCU102 (UltraScale+)
    • ADC: AD9695-625
    • -625 speed grade not supported by HDL
    • clock generation: Synchrona14 (per project wiki)

    so to restate the problem:

    IP block documentation is not clear

    what changes do I need to make to modify the IP block, generated from "util_adxcvr" for the 6.25GHz lane rate, 625MHz adc clock, and 156.25MHz refclk.

    are there any other changes I need to make.

  • Hi,

    The Transceiver Wizard or our script (both described in the wiki page I gave you) reconfigure the transceivers to work at a different lane rate than the maximum one.

    Even if you have the AD9695-625 and you want to use it with the maximum sampling rate, you still need to use this tool to get the configuration that you need to set, because we don't have it in our reference design with 625MHz.

    These parameters need to be changed https://github.com/analogdevicesinc/hdl/blob/main/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl#L71-L99  accordingly to the values that are outputted from either the Transceiver Wizard or the script.

    Table 35 from here might help you, if you want to pick a different configuration.

    It will take some time for me to be able to test this in hardware. I'll try my best to give you a response next week, but I can't promise, as we are short-staffed in this period. Your patience is greatly appreciated.

    In the meantime, please try the script and update those parameters that I mentioned in the link, as many as you can fit.

    Best regards,
    Iulia

  • in the generated project I definitely see lane rates, but no reference click setting other than the divisor settings.

    the script has the devisors, but I dont see any settings for lane rate. so it looks like I should just verify QPLL_FBDIV 40 \ is what I want, and change the lane rate in the generated project. what am I missing? am I overcomplicating this?

    ad_ip_instance util_adxcvr util_ad9695_xcvr [

      list

        RX_NUM_OF_LANES $MAX_RX_NUM_OF_LANES \

        TX_NUM_OF_LANES 0 \

        QPLL_FBDIV 40 \

        QPLL_REFCLK_DIV 1 \

        RX_OUT_DIV 1 \

        RX_CLK25_DIV 13 \

        POR_CFG 0 \

        QPLL_CFG0 13084 \

        QPLL_CFG1 53336 \

        QPLL_CFG1_G3 53336 \

        QPLL_CFG2 4033 \

        QPLL_CFG2_G3 4033 \

        QPLL_CFG3 288 \

        QPLL_CFG4 4 \

        QPLL_CP 255 \

        QPLL_CP_G3 15 \

        QPLL_LPF 831 \

        CH_HSPMUX 17476 \

        PREIQ_FREQ_BST 1 \

        RXPI_CFG0 260 \

        RXPI_CFG1 0 \

        RXCDR_CFG0 3 \

        RXCDR_CFG2_GEN2 613 \

        RXCDR_CFG2_GEN4 356 \

        RXCDR_CFG3 24 \

        RXCDR_CFG3_GEN2 24 \

        RXCDR_CFG3_GEN3 24 \

        RXCDR_CFG3_GEN4 18 \

    ]

    one last thing, im looking at the device tree, it definitely has spi settings for some of the clock frequencies, but I dont see any registers to change this for the ad9695. are these just hooks for the driver? Im having to learn everything at once... 

    ad9695@0 {

    compatible = "adi,ad9695";

    powerdown-gpios = <0x14 0x74 0x00>;

    fastdetect-a-gpios = <0x14 0x71 0x00>;

    fastdetect-b-gpios = <0x14 0x72 0x00>;

    spi-cpol;

    spi-cpha;

    spi-max-frequency = <0x4c4b40>;

    reg = <0x00>;

    clocks = <0x20 0x21 0x22>;

    clock-names = "jesd_adc_clk\0adc_clk\0adc_sysref";

    adi,powerdown-mode = <0x03>;

    adi,sampling-frequency = <0x00 0x2540BE40>; #1,300,000,000  new is 625MHZ 2540BE40

    adi,input-clock-divider-ratio = <0x01>;

    adi,duty-cycle-stabilizer-enable;

    adi,analog-input-neg-buffer-current = <0x1e>;

    adi,analog-input-pos-buffer-current = <0x1e>;

    adi,sysref-lmfc-offset = <0x00>;

    adi,sysref-pos-window-skew = <0x00>;

    adi,sysref-neg-window-skew = <0x00>;

    adi,sysref-mode = <0x01>; # this is contentious mode not jesd mode and shouldn’t effect subclass

    adi,sysref-nshot-ignore-count = <0x00>;

    adi,octets-per-frame = <0x01>;

    adi,frames-per-multiframe = <0x20>;

    adi,converter-resolution = <0x10>;

    adi,bits-per-sample = <0x10>;

    adi,converters-per-device = <0x02>;

    adi,control-bits-per-sample = <0x00>;

    adi,lanes-per-device = <0x04>;

    adi,subclass = <0x00>; # original <0x01>; changing to 0

    #address-cells = <0x01>;

    #size-cells = <0x00>;

    phandle = <0x3f>;

    };

  • Sorry for the late reply, I missed your thread somehow.

    We'll continue the discussion on  gtwizard_generator final steps